[PATCH] D51932: [AMDGPU] Fix-up cases where writelane has 2 SGPR operands

[David Stuttard via Phabricator via llvm-commits]

dstuttard updated this revision to Diff 220667.
dstuttard added a comment.

GFX10 support has gone in since this change was approved - gfx10 allows 2 sgprs
on the constant bus. Implementation updated to allow for this.

Also updated a MIR test that had an incorrect WRITELANE instruction with 2 SGPR
accesses (one of which was VCC_LO).


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D51932/new/

https://reviews.llvm.org/D51932

Files:
  lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SIPeepholeSDWA.cpp
  test/CodeGen/AMDGPU/inserted-wait-states.mir
  test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll

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