[PATCH] D67684: MachineScheduler: Fix missing dependency with multiple subreg defs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: qcolombet.
Herald added subscribers: nhaehnle, wdng, jvesely, MatzeB.

If an instruction had multiple subregister defs, and one of them was
undef, this would improperly conclude all other lanes are
killed. There could still be other defs of those read-undef lanes in
other operands. This would improperly remove register uses from
CurrentVRegUses, so the visitation of later operands would not find
the necessary register dependency. This would also mean this would
fail or not depending on how different subregister def operands were
ordered.

      

On an undef subregister def, scan the instruction for other
subregister defs and avoid killing those.

      

This possibly should be deferring removing anything from
CurrentVRegUses until the entire instruction has been processed
instead.


https://reviews.llvm.org/D67684

Files:
  lib/CodeGen/ScheduleDAGInstrs.cpp
  test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir

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