[PATCH] D66564: [clang-tidy] new FPGA struct pack align check

[Frank Derry Wanye via Phabricator via llvm-commits]

ffrankies added a subscriber: alexandre.isoard.
ffrankies added a comment.
Herald added a subscriber: usaxena95.

@alexandre.isoard wrote:

> I'm not sure what is the advantage of this compared to -Wpadded?


This option only warns when padding exists. Our check does two things; it warns when there is //too much// padding applied to a struct, and when the alignment of the struct isn’t optimal.

In D66564#1670659 <https://reviews.llvm.org/D66564#1670659>, @lebedev.ri wrote:

> I, too, don't believe this is FPGA specific; it should likely go into `misc-` or even `performance-`.


The check can definitely be moved into another module (probably `performance-` is a better bet, since it deals with efficiency).

In D66564#1670659 <https://reviews.llvm.org/D66564#1670659>, @lebedev.ri wrote:

> Forgot the most important question.
>  Right now this will fire on every single struct.
>  But it won't matter unless the alignment/size actually matters, and most often that will happen when you have e.g. a vector of such structs.
>  What i'm asking is - should this be more picky, and complain only about the cases where this matters?


I may need to give some context for this lint check (and the ones to follow, since we have a few others we’d like to upstream once we figure out the process/iron out some bugs).

Our checks are written from the perspective of programmers that write OpenCL code specifically for FPGAs, typically in a SIMD context. There is a compiler framework that performs the necessary compilation for that to work, but due to the nature of the FPGA hardware, it takes a long time for this compilation process to complete. Because of this, it is much preferable to use a static code analysis tool (clang-tidy) to catch errors/inefficiencies in the code before the expensive compilation process starts.

This specific check is based off of the documentation from Intel FPGA SDK for OpenCL Pro Edition: Best Practices Guide <https://www.intel.com/content/www/us/en/programmable/documentation/mwh1391807516407.html#ewa1417026580901>. The TLDR version is that if structs are not aligned and/or padded correctly, the resulting FPGA configuration becomes inefficient.

To answer the question; the size and alignment of the struct will matter when the struct is in an array, but also when the struct’s elements are accessed as part of an uncached loop.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66564/new/

https://reviews.llvm.org/D66564