[PATCH] D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V

[Sam Elliott via Phabricator via llvm-commits]

lenary added a comment.

Two small nits, other than that it's looking pretty good.

I presume you got to the bottom of the exception handling issues you saw, and they are now solved.



================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:501
+
+  // First we need to filter out candidates where the X5 register can't be used
+  // to setup the function call.
----------------
It would be useful to include the ABI name of x5 in this comment too.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:503
+  // to setup the function call.
+  auto CantInsertCall = [](outliner::Candidate &C) {
+    const TargetRegisterInfo *TRI = C.getMF()->getSubtarget().getRegisterInfo();
----------------
Can you rename this to `CannotInsertCall`, I kept missing the `t` when reviewing, which inverts its meaning.


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https://reviews.llvm.org/D66210