[llvm] r372113 - Hide implementation details in namespaces.
Benjamin Kramer via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 17 05:56:30 PDT 2019
Author: d0k
Date: Tue Sep 17 05:56:29 2019
New Revision: 372113
URL: http://llvm.org/viewvc/llvm-project?rev=372113&view=rev
Log:
Hide implementation details in namespaces.
Modified:
llvm/trunk/lib/CodeGen/MIRVRegNamerUtils.h
llvm/trunk/lib/CodeGen/ModuloSchedule.cpp
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/trunk/lib/Target/ARM/MVEVPTBlockPass.cpp
llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
llvm/trunk/lib/Transforms/IPO/Attributor.cpp
Modified: llvm/trunk/lib/CodeGen/MIRVRegNamerUtils.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRVRegNamerUtils.h?rev=372113&r1=372112&r2=372113&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRVRegNamerUtils.h (original)
+++ llvm/trunk/lib/CodeGen/MIRVRegNamerUtils.h Tue Sep 17 05:56:29 2019
@@ -1,3 +1,4 @@
+
//===------------ MIRVRegNamerUtils.h - MIR VReg Renaming Utilities -------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
@@ -13,6 +14,9 @@
//
//===----------------------------------------------------------------------===//
+#ifndef LLVM_LIB_CODEGEN_MIRVREGNAMERUTILS_H
+#define LLVM_LIB_CODEGEN_MIRVREGNAMERUTILS_H
+
#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
@@ -23,7 +27,7 @@
#include <queue>
-using namespace llvm;
+namespace llvm {
/// NamedVRegCursor - The cursor is an object that keeps track of what the next
/// vreg name should be. It does book keeping to determine when to skip the
@@ -81,3 +85,7 @@ public:
// @return changed
bool renameVRegs(MachineBasicBlock *MBB);
};
+
+} // namespace llvm
+
+#endif
Modified: llvm/trunk/lib/CodeGen/ModuloSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ModuloSchedule.cpp?rev=372113&r1=372112&r2=372113&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ModuloSchedule.cpp (original)
+++ llvm/trunk/lib/CodeGen/ModuloSchedule.cpp Tue Sep 17 05:56:29 2019
@@ -1667,6 +1667,7 @@ void PeelingModuloScheduleExpander::vali
// "Stage=%d Cycle=%d".
//===----------------------------------------------------------------------===//
+namespace {
class ModuloScheduleTest : public MachineFunctionPass {
public:
static char ID;
@@ -1684,6 +1685,7 @@ public:
MachineFunctionPass::getAnalysisUsage(AU);
}
};
+} // namespace
char ModuloScheduleTest::ID = 0;
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=372113&r1=372112&r2=372113&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Sep 17 05:56:29 2019
@@ -5843,7 +5843,7 @@ enum PredicateConstraint {
Invalid
};
-PredicateConstraint parsePredicateConstraint(StringRef Constraint) {
+static PredicateConstraint parsePredicateConstraint(StringRef Constraint) {
PredicateConstraint P = PredicateConstraint::Invalid;
if (Constraint == "Upa")
P = PredicateConstraint::Upa;
Modified: llvm/trunk/lib/Target/ARM/MVEVPTBlockPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MVEVPTBlockPass.cpp?rev=372113&r1=372112&r2=372113&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MVEVPTBlockPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MVEVPTBlockPass.cpp Tue Sep 17 05:56:29 2019
@@ -80,7 +80,7 @@ enum VPTMaskValue {
TETE = 15 // 0b1111
};
-unsigned VCMPOpcodeToVPT(unsigned Opcode) {
+static unsigned VCMPOpcodeToVPT(unsigned Opcode) {
switch (Opcode) {
case ARM::MVE_VCMPf32:
return ARM::MVE_VPTv4f32;
@@ -133,9 +133,9 @@ unsigned VCMPOpcodeToVPT(unsigned Opcode
}
}
-MachineInstr *findVCMPToFoldIntoVPST(MachineBasicBlock::iterator MI,
- const TargetRegisterInfo *TRI,
- unsigned &NewOpcode) {
+static MachineInstr *findVCMPToFoldIntoVPST(MachineBasicBlock::iterator MI,
+ const TargetRegisterInfo *TRI,
+ unsigned &NewOpcode) {
// Search backwards to the instruction that defines VPR. This may or not
// be a VCMP, we check that after this loop. If we find another instruction
// that reads cpsr, we return nullptr.
Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=372113&r1=372112&r2=372113&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Tue Sep 17 05:56:29 2019
@@ -2552,8 +2552,8 @@ static unsigned getHiPELiteral(
// Return true if there are no non-ehpad successors to MBB and there are no
// non-meta instructions between MBBI and MBB.end().
-bool blockEndIsUnreachable(const MachineBasicBlock &MBB,
- MachineBasicBlock::const_iterator MBBI) {
+static bool blockEndIsUnreachable(const MachineBasicBlock &MBB,
+ MachineBasicBlock::const_iterator MBBI) {
return std::all_of(
MBB.succ_begin(), MBB.succ_end(),
[](const MachineBasicBlock *Succ) { return Succ->isEHPad(); }) &&
Modified: llvm/trunk/lib/Transforms/IPO/Attributor.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/Attributor.cpp?rev=372113&r1=372112&r2=372113&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/Attributor.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/Attributor.cpp Tue Sep 17 05:56:29 2019
@@ -161,7 +161,7 @@ ChangeStatus llvm::operator&(ChangeStatu
/// limit how much effort is invested, we will never visit more values than
/// specified by \p MaxValues.
template <typename AAType, typename StateTy>
-bool genericValueTraversal(
+static bool genericValueTraversal(
Attributor &A, IRPosition IRP, const AAType &QueryingAA, StateTy &State,
const function_ref<bool(Value &, StateTy &, bool)> &VisitValueCB,
int MaxValues = 8) {
@@ -486,6 +486,7 @@ void IRPosition::verify() {
}
}
+namespace {
/// Helper functions to clamp a state \p S of type \p StateType with the
/// information in \p R and indicate/return if \p S did change (as-in update is
/// required to be run again).
@@ -3406,6 +3407,7 @@ struct AAHeapToStackFunction final : pub
BUILD_STAT_NAME(MallocCalls, Function) += MallocCalls.size();
}
};
+} // namespace
/// ----------------------------------------------------------------------------
/// Attributor
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