[PATCH] D67327: [ARM] Fix for MVE narrow load/store stack accesses

[Dave Green via Phabricator via llvm-commits]

dmgreen updated this revision to Diff 220467.
dmgreen added a comment.

The widening/narrowing MVE loads and stores, like MVE_VLDRBU32 (the B with the 32, in this example) can only take "thumb" registers as they only have 3 bits for the Rn operand. Which is what I meant by "can't take SP". This is not something that any other stack load/store has had to deal with in the past, and hence RegClass->contains(ARM::SP) is added here to check for such cases. Similar to https://reviews.llvm.org/D66285.

The other MVE loads/stores, like a MVE_VLDRBU8 do have the full 4 bits needed for "Thumb2" register, so do not hit the same problem. They can accept a SP and it will only be a problem for frame indices if the offset is out of range of the instruction.

I've added another test for that second case.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67327/new/

https://reviews.llvm.org/D67327

Files:
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/test/CodeGen/Thumb2/mve-stacksplot.mir

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