[PATCH] D67489: [ARM] Add a SelectTAddrModeImm7 for MVE narrow loads and stores

[Dave Green via Phabricator via llvm-commits]

dmgreen marked 3 inline comments as done.
dmgreen added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1159
+                                          SDValue &OffImm) {
+  if (N.getOpcode() == ISD::SUB || CurDAG->isBaseWithConstantOffset(N)) {
+    int RHSC;
----------------
samparker wrote:
> What happens if N == ISD::ADD?
Oh, i forgot to mention that this is just a copy of SelectT2AddrModeImm7, with the part about FrameIndex's removed. The other code is the same, so I hope will work as well as it did before.

I think isBaseWithConstantOffset will handle adds (and or's where we know the alignment). We just don't negate the RHSC.


================
Comment at: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1285
 template <unsigned Shift>
 bool ARMDAGToDAGISel::SelectT2AddrModeImm7(SDValue N, SDValue &Base,
                                            SDValue &OffImm) {
----------------
This one.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67489/new/

https://reviews.llvm.org/D67489