[llvm] r371991 - AMDGPU/GlobalISel: Fix RegBankSelect for G_FRINT and G_FCEIL
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 16 07:14:37 PDT 2019
Author: arsenm
Date: Mon Sep 16 07:14:37 2019
New Revision: 371991
URL: http://llvm.org/viewvc/llvm-project?rev=371991&view=rev
Log:
AMDGPU/GlobalISel: Fix RegBankSelect for G_FRINT and G_FCEIL
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frint.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=371991&r1=371990&r2=371991&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Mon Sep 16 07:14:37 2019
@@ -1783,6 +1783,8 @@ AMDGPURegisterBankInfo::getInstrMapping(
case AMDGPU::G_FMAD:
case AMDGPU::G_FSQRT:
case AMDGPU::G_FFLOOR:
+ case AMDGPU::G_FCEIL:
+ case AMDGPU::G_FRINT:
case AMDGPU::G_SITOFP:
case AMDGPU::G_UITOFP:
case AMDGPU::G_FPTRUNC:
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir?rev=371991&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir Mon Sep 16 07:14:37 2019
@@ -0,0 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+---
+name: fceil_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: fceil_s
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK: [[FCEIL_:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = G_FCEIL %0
+...
+
+---
+name: fceil_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; CHECK-LABEL: name: fceil_v
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK: [[FCEIL_:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = G_FCEIL %0
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frint.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frint.mir?rev=371991&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frint.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frint.mir Mon Sep 16 07:14:37 2019
@@ -0,0 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+---
+name: frint_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: frint_s
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK: [[FRINT_:%[0-9]+]]:vgpr(s32) = G_FRINT [[COPY]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = G_FRINT %0
+...
+
+---
+name: frint_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; CHECK-LABEL: name: frint_v
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK: [[FRINT_:%[0-9]+]]:vgpr(s32) = G_FRINT [[COPY]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = G_FRINT %0
+...
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