[llvm] r371949 - AMDGPU/GlobalISel: Select s32->s16 G_[US]ITOFP
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 15 17:29:12 PDT 2019
Author: arsenm
Date: Sun Sep 15 17:29:12 2019
New Revision: 371949
URL: http://llvm.org/viewvc/llvm-project?rev=371949&view=rev
Log:
AMDGPU/GlobalISel: Select s32->s16 G_[US]ITOFP
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=371949&r1=371948&r2=371949&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Sun Sep 15 17:29:12 2019
@@ -753,12 +753,12 @@ def : GCNPat <
def : GCNPat <
(f16 (sint_to_fp i32:$src)),
- (V_CVT_F16_F32_e32 (V_CVT_F32_I32_e32 $src))
+ (V_CVT_F16_F32_e32 (V_CVT_F32_I32_e32 VSrc_b32:$src))
>;
def : GCNPat <
(f16 (uint_to_fp i32:$src)),
- (V_CVT_F16_F32_e32 (V_CVT_F32_U32_e32 $src))
+ (V_CVT_F16_F32_e32 (V_CVT_F32_U32_e32 VSrc_b32:$src))
>;
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir?rev=371949&r1=371948&r2=371949&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir Sun Sep 15 17:29:12 2019
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
---
@@ -6,27 +7,74 @@ name: sitofp
legalized: true
regBankSelected: true
-# GCN-LABEL: name: sitofp
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4
- ; GCN: [[SGPR:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN-LABEL: name: sitofp
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
+ ; GCN: [[V_CVT_F32_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY]], 0, 0, implicit $exec
+ ; GCN: [[V_CVT_F32_I32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY1]], 0, 0, implicit $exec
+ ; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
+ ; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
%0:sgpr(s32) = COPY $sgpr0
- ; GCN: [[VGPR:%[0-9]+]]:vgpr_32 = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(p1) = COPY $vgpr3_vgpr4
; sitofp s
- ; GCN: V_CVT_F32_I32_e64 [[SGPR]], 0, 0
%3:vgpr(s32) = G_SITOFP %0
; sitofp v
- ; GCN: V_CVT_F32_I32_e64 [[VGPR]], 0, 0
%4:vgpr(s32) = G_SITOFP %1
G_STORE %3, %2 :: (store 4, addrspace 1)
G_STORE %4, %2 :: (store 4, addrspace 1)
...
+
+---
+name: sitofp_s32_to_s16_vv
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; GCN-LABEL: name: sitofp_s32_to_s16_vv
+ ; GCN: liveins: $vgpr0
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec
+ ; GCN: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec
+ ; GCN: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s16) = G_SITOFP %0
+ %2:vgpr(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: sitofp_s32_to_s16_vs
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; GCN-LABEL: name: sitofp_s32_to_s16_vs
+ ; GCN: liveins: $sgpr0
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec
+ ; GCN: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec
+ ; GCN: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:vgpr(s16) = G_SITOFP %0
+ %2:vgpr(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir?rev=371949&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir Sun Sep 15 17:29:12 2019
@@ -0,0 +1,86 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
+
+---
+name: uitofp_s32_to_s32_vv
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; GCN-LABEL: name: uitofp_s32_to_s32_vv
+ ; GCN: liveins: $vgpr0
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec
+ ; GCN: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = G_UITOFP %0
+ $vgpr0 = COPY %1
+...
+
+---
+name: uitofp_s32_to_s32_vs
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; GCN-LABEL: name: uitofp_s32_to_s32_vs
+ ; GCN: liveins: $sgpr0
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec
+ ; GCN: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:vgpr(s32) = G_UITOFP %0
+ $vgpr0 = COPY %1
+...
+
+---
+name: uitofp_s32_to_s16_vv
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; GCN-LABEL: name: uitofp_s32_to_s16_vv
+ ; GCN: liveins: $vgpr0
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec
+ ; GCN: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec
+ ; GCN: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s16) = G_UITOFP %0
+ %2:vgpr(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: uitofp_s32_to_s16_vs
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; GCN-LABEL: name: uitofp_s32_to_s16_vs
+ ; GCN: liveins: $sgpr0
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec
+ ; GCN: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec
+ ; GCN: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:vgpr(s16) = G_UITOFP %0
+ %2:vgpr(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir?rev=371949&r1=371948&r2=371949&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir Sun Sep 15 17:29:12 2019
@@ -143,12 +143,12 @@ body: |
...
---
-name: test_sitofp_s32_to_s16
+name: test_sitofp_s16_to_s32
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: test_sitofp_s32_to_s16
+ ; CHECK-LABEL: name: test_sitofp_s16_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[COPY]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SITOFP]](s16)
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir?rev=371949&r1=371948&r2=371949&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir Sun Sep 15 17:29:12 2019
@@ -112,12 +112,12 @@ body: |
...
---
-name: test_uitofp_s32_to_s16
+name: test_uitofp_s16_to_s32
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: test_uitofp_s32_to_s16
+ ; CHECK-LABEL: name: test_uitofp_s16_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[COPY]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UITOFP]](s16)
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