[llvm] r371906 - [WebAssembly] Narrowing and widening SIMD ops
Thomas Lively via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 13 15:54:41 PDT 2019
Author: tlively
Date: Fri Sep 13 15:54:41 2019
New Revision: 371906
URL: http://llvm.org/viewvc/llvm-project?rev=371906&view=rev
Log:
[WebAssembly] Narrowing and widening SIMD ops
Summary:
Implements target-specific LLVM intrinsics and clang builtins for
these new SIMD operations, as described at https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#integer-to-integer-narrowing.
Reviewers: aheejin
Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D67425
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td
llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll
llvm/trunk/test/MC/WebAssembly/simd-encodings.s
Modified: llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td?rev=371906&r1=371905&r2=371906&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td Fri Sep 13 15:54:41 2019
@@ -117,6 +117,31 @@ def int_wasm_qfms :
Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem, IntrSpeculatable]>;
+def int_wasm_narrow_signed :
+ Intrinsic<[llvm_anyvector_ty],
+ [llvm_anyvector_ty, LLVMMatchType<1>],
+ [IntrNoMem, IntrSpeculatable]>;
+def int_wasm_narrow_unsigned :
+ Intrinsic<[llvm_anyvector_ty],
+ [llvm_anyvector_ty, LLVMMatchType<1>],
+ [IntrNoMem, IntrSpeculatable]>;
+def int_wasm_widen_low_signed :
+ Intrinsic<[llvm_anyvector_ty],
+ [llvm_anyvector_ty],
+ [IntrNoMem, IntrSpeculatable]>;
+def int_wasm_widen_high_signed :
+ Intrinsic<[llvm_anyvector_ty],
+ [llvm_anyvector_ty],
+ [IntrNoMem, IntrSpeculatable]>;
+def int_wasm_widen_low_unsigned :
+ Intrinsic<[llvm_anyvector_ty],
+ [llvm_anyvector_ty],
+ [IntrNoMem, IntrSpeculatable]>;
+def int_wasm_widen_high_unsigned :
+ Intrinsic<[llvm_anyvector_ty],
+ [llvm_anyvector_ty],
+ [IntrNoMem, IntrSpeculatable]>;
+
//===----------------------------------------------------------------------===//
// Bulk memory intrinsics
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td?rev=371906&r1=371905&r2=371906&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td Fri Sep 13 15:54:41 2019
@@ -712,6 +712,42 @@ defm "" : SIMDConvert<v4i32, v4f32, fp_t
defm "" : SIMDConvert<v2i64, v2f64, fp_to_sint, "i64x2.trunc_sat_f64x2_s", 173>;
defm "" : SIMDConvert<v2i64, v2f64, fp_to_uint, "i64x2.trunc_sat_f64x2_u", 174>;
+// Widening operations
+multiclass SIMDWiden<ValueType vec_t, string vec, ValueType arg_t, string arg,
+ bits<32> baseInst> {
+ defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_low_signed,
+ vec#".widen_low_"#arg#"_s", baseInst>;
+ defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_high_signed,
+ vec#".widen_high_"#arg#"_s", !add(baseInst, 1)>;
+ defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_low_unsigned,
+ vec#".widen_low_"#arg#"_u", !add(baseInst, 2)>;
+ defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_high_unsigned,
+ vec#".widen_high_"#arg#"_u", !add(baseInst, 3)>;
+}
+
+defm "" : SIMDWiden<v8i16, "i16x8", v16i8, "i8x16", 202>;
+defm "" : SIMDWiden<v4i32, "i32x4", v8i16, "i16x8", 206>;
+
+// Narrowing operations
+multiclass SIMDNarrow<ValueType vec_t, string vec, ValueType arg_t, string arg,
+ bits<32> baseInst> {
+ defm NARROW_S_#vec_t :
+ SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
+ [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_signed
+ (arg_t V128:$low), (arg_t V128:$high))))],
+ vec#".narrow_"#arg#"_s\t$dst, $low, $high", vec#".narrow_"#arg#"_s",
+ baseInst>;
+ defm NARROW_U_#vec_t :
+ SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
+ [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_unsigned
+ (arg_t V128:$low), (arg_t V128:$high))))],
+ vec#".narrow_"#arg#"_u\t$dst, $low, $high", vec#".narrow_"#arg#"_u",
+ !add(baseInst, 1)>;
+}
+
+defm "" : SIMDNarrow<v16i8, "i8x16", v8i16, "i16x8", 198>;
+defm "" : SIMDNarrow<v8i16, "i16x8", v4i32, "i32x4", 200>;
+
// Lower llvm.wasm.trunc.saturate.* to saturating instructions
def : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))),
(fp_to_sint_v4i32_v4f32 (v4f32 V128:$src))>;
Modified: llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll?rev=371906&r1=371905&r2=371906&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll Fri Sep 13 15:54:41 2019
@@ -87,6 +87,30 @@ define <16 x i8> @bitselect_v16i8(<16 x
ret <16 x i8> %a
}
+; CHECK-LABEL: narrow_signed_v16i8:
+; SIMD128-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}}
+; SIMD128-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(<8 x i16>, <8 x i16>)
+define <16 x i8> @narrow_signed_v16i8(<8 x i16> %low, <8 x i16> %high) {
+ %a = call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(
+ <8 x i16> %low, <8 x i16> %high
+ )
+ ret <16 x i8> %a
+}
+
+; CHECK-LABEL: narrow_unsigned_v16i8:
+; SIMD128-NEXT: .functype narrow_unsigned_v16i8 (v128, v128) -> (v128){{$}}
+; SIMD128-NEXT: i8x16.narrow_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(<8 x i16>, <8 x i16>)
+define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) {
+ %a = call <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(
+ <8 x i16> %low, <8 x i16> %high
+ )
+ ret <16 x i8> %a
+}
+
; ==============================================================================
; 8 x i16
; ==============================================================================
@@ -166,6 +190,70 @@ define <8 x i16> @bitselect_v8i16(<8 x i
ret <8 x i16> %a
}
+; CHECK-LABEL: narrow_signed_v8i16:
+; SIMD128-NEXT: .functype narrow_signed_v8i16 (v128, v128) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.narrow_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(<4 x i32>, <4 x i32>)
+define <8 x i16> @narrow_signed_v8i16(<4 x i32> %low, <4 x i32> %high) {
+ %a = call <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(
+ <4 x i32> %low, <4 x i32> %high
+ )
+ ret <8 x i16> %a
+}
+
+; CHECK-LABEL: narrow_unsigned_v8i16:
+; SIMD128-NEXT: .functype narrow_unsigned_v8i16 (v128, v128) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.narrow_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(<4 x i32>, <4 x i32>)
+define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) {
+ %a = call <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(
+ <4 x i32> %low, <4 x i32> %high
+ )
+ ret <8 x i16> %a
+}
+
+; CHECK-LABEL: widen_low_signed_v8i16:
+; SIMD128-NEXT: .functype widen_low_signed_v8i16 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.widen_low_i8x16_s $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <8 x i16> @llvm.wasm.widen.low.signed.v8i16.v16i8(<16 x i8>)
+define <8 x i16> @widen_low_signed_v8i16(<16 x i8> %v) {
+ %a = call <8 x i16> @llvm.wasm.widen.low.signed.v8i16.v16i8(<16 x i8> %v)
+ ret <8 x i16> %a
+}
+
+; CHECK-LABEL: widen_high_signed_v8i16:
+; SIMD128-NEXT: .functype widen_high_signed_v8i16 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.widen_high_i8x16_s $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <8 x i16> @llvm.wasm.widen.high.signed.v8i16.v16i8(<16 x i8>)
+define <8 x i16> @widen_high_signed_v8i16(<16 x i8> %v) {
+ %a = call <8 x i16> @llvm.wasm.widen.high.signed.v8i16.v16i8(<16 x i8> %v)
+ ret <8 x i16> %a
+}
+
+; CHECK-LABEL: widen_low_unsigned_v8i16:
+; SIMD128-NEXT: .functype widen_low_unsigned_v8i16 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.widen_low_i8x16_u $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <8 x i16> @llvm.wasm.widen.low.unsigned.v8i16.v16i8(<16 x i8>)
+define <8 x i16> @widen_low_unsigned_v8i16(<16 x i8> %v) {
+ %a = call <8 x i16> @llvm.wasm.widen.low.unsigned.v8i16.v16i8(<16 x i8> %v)
+ ret <8 x i16> %a
+}
+
+; CHECK-LABEL: widen_high_unsigned_v8i16:
+; SIMD128-NEXT: .functype widen_high_unsigned_v8i16 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.widen_high_i8x16_u $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <8 x i16> @llvm.wasm.widen.high.unsigned.v8i16.v16i8(<16 x i8>)
+define <8 x i16> @widen_high_unsigned_v8i16(<16 x i8> %v) {
+ %a = call <8 x i16> @llvm.wasm.widen.high.unsigned.v8i16.v16i8(<16 x i8> %v)
+ ret <8 x i16> %a
+}
+
; ==============================================================================
; 4 x i32
; ==============================================================================
@@ -223,6 +311,46 @@ define <4 x i32> @trunc_sat_u_v4i32(<4 x
ret <4 x i32> %a
}
+; CHECK-LABEL: widen_low_signed_v4i32:
+; SIMD128-NEXT: .functype widen_low_signed_v4i32 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.widen_low_i16x8_s $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.widen.low.signed.v4i32.v8i16(<8 x i16>)
+define <4 x i32> @widen_low_signed_v4i32(<8 x i16> %v) {
+ %a = call <4 x i32> @llvm.wasm.widen.low.signed.v4i32.v8i16(<8 x i16> %v)
+ ret <4 x i32> %a
+}
+
+; CHECK-LABEL: widen_high_signed_v4i32:
+; SIMD128-NEXT: .functype widen_high_signed_v4i32 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.widen_high_i16x8_s $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.widen.high.signed.v4i32.v8i16(<8 x i16>)
+define <4 x i32> @widen_high_signed_v4i32(<8 x i16> %v) {
+ %a = call <4 x i32> @llvm.wasm.widen.high.signed.v4i32.v8i16(<8 x i16> %v)
+ ret <4 x i32> %a
+}
+
+; CHECK-LABEL: widen_low_unsigned_v4i32:
+; SIMD128-NEXT: .functype widen_low_unsigned_v4i32 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.widen_low_i16x8_u $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.widen.low.unsigned.v4i32.v8i16(<8 x i16>)
+define <4 x i32> @widen_low_unsigned_v4i32(<8 x i16> %v) {
+ %a = call <4 x i32> @llvm.wasm.widen.low.unsigned.v4i32.v8i16(<8 x i16> %v)
+ ret <4 x i32> %a
+}
+
+; CHECK-LABEL: widen_high_unsigned_v4i32:
+; SIMD128-NEXT: .functype widen_high_unsigned_v4i32 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.widen_high_i16x8_u $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.widen.high.unsigned.v4i32.v8i16(<8 x i16>)
+define <4 x i32> @widen_high_unsigned_v4i32(<8 x i16> %v) {
+ %a = call <4 x i32> @llvm.wasm.widen.high.unsigned.v4i32.v8i16(<8 x i16> %v)
+ ret <4 x i32> %a
+}
+
; ==============================================================================
; 2 x i64
; ==============================================================================
Modified: llvm/trunk/test/MC/WebAssembly/simd-encodings.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/WebAssembly/simd-encodings.s?rev=371906&r1=371905&r2=371906&view=diff
==============================================================================
--- llvm/trunk/test/MC/WebAssembly/simd-encodings.s (original)
+++ llvm/trunk/test/MC/WebAssembly/simd-encodings.s Fri Sep 13 15:54:41 2019
@@ -463,4 +463,40 @@ main:
# CHECK: f64x2.convert_i64x2_u # encoding: [0xfd,0xb2,0x01]
f64x2.convert_i64x2_u
+ # CHECK: i8x16.narrow_i16x8_s # encoding: [0xfd,0xc6,0x01]
+ i8x16.narrow_i16x8_s
+
+ # CHECK: i8x16.narrow_i16x8_u # encoding: [0xfd,0xc7,0x01]
+ i8x16.narrow_i16x8_u
+
+ # CHECK: i16x8.narrow_i32x4_s # encoding: [0xfd,0xc8,0x01]
+ i16x8.narrow_i32x4_s
+
+ # CHECK: i16x8.narrow_i32x4_u # encoding: [0xfd,0xc9,0x01]
+ i16x8.narrow_i32x4_u
+
+ # CHECK: i16x8.widen_low_i8x16_s # encoding: [0xfd,0xca,0x01]
+ i16x8.widen_low_i8x16_s
+
+ # CHECK: i16x8.widen_high_i8x16_s # encoding: [0xfd,0xcb,0x01]
+ i16x8.widen_high_i8x16_s
+
+ # CHECK: i16x8.widen_low_i8x16_u # encoding: [0xfd,0xcc,0x01]
+ i16x8.widen_low_i8x16_u
+
+ # CHECK: i16x8.widen_high_i8x16_u # encoding: [0xfd,0xcd,0x01]
+ i16x8.widen_high_i8x16_u
+
+ # CHECK: i32x4.widen_low_i16x8_s # encoding: [0xfd,0xce,0x01]
+ i32x4.widen_low_i16x8_s
+
+ # CHECK: i32x4.widen_high_i16x8_s # encoding: [0xfd,0xcf,0x01]
+ i32x4.widen_high_i16x8_s
+
+ # CHECK: i32x4.widen_low_i16x8_u # encoding: [0xfd,0xd0,0x01]
+ i32x4.widen_low_i16x8_u
+
+ # CHECK: i32x4.widen_high_i16x8_u # encoding: [0xfd,0xd1,0x01]
+ i32x4.widen_high_i16x8_u
+
end_function
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