[PATCH] D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill updated this revision to Diff 220069.
lewis-revill added a comment.

Refactor the MIR test case again:

- use `-run-pass=machine-outliner` to only test this pass (required removing the no-machineoutliner checks, they are redundant anyway)
- add riscv64 checks for completeness?
- add `-verify-machineinstrs`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66210/new/

https://reviews.llvm.org/D66210

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/machineoutliner.mir

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