[llvm] r371857 - [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC
Jinsong Ji via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 13 07:18:36 PDT 2019
Author: jsji
Date: Fri Sep 13 07:18:36 2019
New Revision: 371857
URL: http://llvm.org/viewvc/llvm-project?rev=371857&view=rev
Log:
[PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC
All tests with -run-pass !=none should not in MIR/, See MIR/README.
```
Tests for codegen passes should NOT be here but in
test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.
```
Added:
llvm/trunk/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir
llvm/trunk/test/CodeGen/PowerPC/machine-backward-cp.mir
llvm/trunk/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
llvm/trunk/test/CodeGen/PowerPC/prolog_vec_spills.mir
Removed:
llvm/trunk/test/CodeGen/MIR/PowerPC/ifcvt-diamond-ret.mir
llvm/trunk/test/CodeGen/MIR/PowerPC/machine-backward-cp.mir
llvm/trunk/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir
llvm/trunk/test/CodeGen/MIR/PowerPC/prolog_vec_spills.mir
Removed: llvm/trunk/test/CodeGen/MIR/PowerPC/ifcvt-diamond-ret.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/PowerPC/ifcvt-diamond-ret.mir?rev=371856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/PowerPC/ifcvt-diamond-ret.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/PowerPC/ifcvt-diamond-ret.mir (removed)
@@ -1,34 +0,0 @@
-# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -run-pass=if-converter %s -o - | FileCheck %s
----
-name: foo
-body: |
- bb.0:
- liveins: $x0, $x3
- successors: %bb.1(0x40000000), %bb.2(0x40000000)
-
- dead renamable $x3 = ANDIo8 killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
- $cr2lt = CROR $cr0gt, $cr0gt
- BCn killed renamable $cr2lt, %bb.2
- B %bb.1
-
- bb.1:
- renamable $x3 = LIS8 4096
- MTLR8 $x0, implicit-def $lr8
- BLR8 implicit $lr8, implicit $rm, implicit $x3
-
- bb.2:
- renamable $x3 = LIS8 4096
- MTLR8 $x0, implicit-def $lr8
- BLR8 implicit $lr8, implicit $rm, implicit $x3
-...
-
-# Diamond testcase with equivalent branches terminating in returns.
-
-# CHECK: body: |
-# CHECK: bb.0:
-# CHECK: dead renamable $x3 = ANDIo8 killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
-# CHECK: $cr2lt = CROR $cr0gt, $cr0gt
-# CHECK: renamable $x3 = LIS8 4096
-# CHECK: MTLR8 $x0, implicit-def $lr8
-# CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
-
Removed: llvm/trunk/test/CodeGen/MIR/PowerPC/machine-backward-cp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/PowerPC/machine-backward-cp.mir?rev=371856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/PowerPC/machine-backward-cp.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/PowerPC/machine-backward-cp.mir (removed)
@@ -1,281 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O3 -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
-# RUN: -mcpu=pwr9 -simplify-mir -run-pass=machine-cp %s -o - | FileCheck %s
-
-# Normal case
----
-name: test0
-alignment: 4
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test0
- ; CHECK: renamable $x4 = LI8 1024
- ; CHECK: $x3 = COPY killed renamable $x4
- ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
- renamable $x4 = LI8 1024
- $x3 = COPY renamable killed $x4
- BLR8 implicit $lr8, implicit undef $rm, implicit $x3
-
-...
-
-# Not in terminal BBs
----
-name: test1
-alignment: 4
-tracksRegLiveness: true
-body: |
- ; CHECK-LABEL: name: test1
- ; CHECK: bb.0.entry:
- ; CHECK: renamable $x5 = LI8 42
- ; CHECK: renamable $x4 = COPY killed renamable $x5
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: liveins: $x4
- ; CHECK: $x3 = COPY killed renamable $x4
- ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
- bb.0.entry:
- successors: %bb.1
-
- renamable $x5 = LI8 42
- renamable $x4 = COPY renamable killed $x5
- B %bb.1
-
- bb.1:
- liveins: $x4
- $x3 = COPY renamable killed $x4
- BLR8 implicit $lr8, implicit undef $rm, implicit $x3
-
-...
-
-# Use reserved register
----
-name: test2
-alignment: 4
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test2
- ; CHECK: renamable $x4 = LI8 1024
- ; CHECK: $x13 = COPY killed renamable $x4
- ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit undef $x3
- renamable $x4 = LI8 1024
- $x13 = COPY renamable killed $x4
- BLR8 implicit $lr8, implicit undef $rm, implicit undef $x3
-
-...
-
-# Intermediate read of copy's src
----
-name: test3
-alignment: 4
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test3
- ; CHECK: renamable $x4 = LI8 0
- ; CHECK: renamable $x5 = ADDI8 $x4, 1
- ; CHECK: $x3 = COPY killed renamable $x4
- ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
- renamable $x4 = LI8 0
- renamable $x5 = ADDI8 $x4, 1
- $x3 = COPY renamable killed $x4
- BLR8 implicit $lr8, implicit undef $rm, implicit $x3
-
-...
-
-# Intermediate read of copy's def
----
-name: test4
-alignment: 4
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x3
-
- ; CHECK-LABEL: name: test4
- ; CHECK: liveins: $x3
- ; CHECK: renamable $x4 = LI8 0
- ; CHECK: renamable $x5 = ADDI8 $x3, 1
- ; CHECK: $x3 = COPY killed renamable $x4
- ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
- renamable $x4 = LI8 0
- renamable $x5 = ADDI8 $x3, 1
- $x3 = COPY renamable killed $x4
- BLR8 implicit $lr8, implicit undef $rm, implicit $x3
-
-...
-
-# Intermiediate clobber of copy's def
----
-name: test5
-alignment: 4
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x3, $x5
-
- ; CHECK-LABEL: name: test5
- ; CHECK: liveins: $x3, $x5
- ; CHECK: renamable $x4 = LI8 0
- ; CHECK: renamable $x3 = ADDI8 $x5, 1
- ; CHECK: $x3 = COPY killed renamable $x4
- ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
- renamable $x4 = LI8 0
- renamable $x3 = ADDI8 $x5, 1
- $x3 = COPY renamable killed $x4
- BLR8 implicit $lr8, implicit undef $rm, implicit $x3
-
-...
-
----
-name: iterative_deletion
-alignment: 4
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x5
-
- ; CHECK-LABEL: name: iterative_deletion
- ; CHECK: liveins: $x5
- ; CHECK: renamable $x6 = ADDI8 killed renamable $x5, 1
- ; CHECK: $x3 = COPY $x6
- ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
- renamable $x6 = ADDI8 renamable killed $x5, 1
- renamable $x4 = COPY renamable killed $x6
- renamable $x7 = COPY renamable killed $x4
- $x3 = COPY renamable killed $x7
- BLR8 implicit $lr8, implicit undef $rm, implicit $x3
-
-...
-
----
-name: Enter
-alignment: 4
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x4, $x7
- ; CHECK-LABEL: name: Enter
- ; CHECK: liveins: $x4, $x7
- ; CHECK: renamable $x5 = COPY killed renamable $x7
- ; CHECK: renamable $x6 = ADDI8 killed renamable $x4, 1
- ; CHECK: $x3 = ADD8 killed renamable $x5, $x6
- ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
- renamable $x5 = COPY killed renamable $x7
- renamable $x6 = ADDI8 killed renamable $x4, 1
- renamable $x7 = COPY killed renamable $x6
- $x3 = ADD8 renamable killed $x5, renamable killed $x7
- BLR8 implicit $lr8, implicit undef $rm, implicit $x3
-
-...
-
----
-name: foo
-alignment: 4
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x4, $x7
- ; CHECK-LABEL: name: foo
- ; CHECK: liveins: $x4, $x7
- ; CHECK: renamable $x5 = COPY killed renamable $x7
- ; CHECK: renamable $x6 = ADDI8 renamable $x4, 1
- ; CHECK: renamable $x7 = COPY killed renamable $x6
- ; CHECK: renamable $x8 = ADDI8 killed $x4, 2
- ; CHECK: $x3 = ADD8 killed renamable $x5, $x8
- ; CHECK: $x3 = ADD8 $x3, killed renamable $x7
- ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
- renamable $x5 = COPY killed renamable $x7
- renamable $x6 = ADDI8 renamable $x4, 1
- renamable $x7 = COPY killed renamable $x6
- renamable $x8 = ADDI8 killed $x4, 2
- renamable $x6 = COPY killed renamable $x8
- $x3 = ADD8 renamable killed $x5, renamable killed $x6
- $x3 = ADD8 $x3, renamable killed $x7
- BLR8 implicit $lr8, implicit undef $rm, implicit $x3
-
-...
-
----
-name: bar
-alignment: 4
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x4, $x7
- ; CHECK-LABEL: name: bar
- ; CHECK: liveins: $x4, $x7
- ; CHECK: renamable $x5 = COPY killed renamable $x7
- ; CHECK: renamable $x6 = ADDI8 renamable $x4, 1
- ; CHECK: renamable $x8 = COPY $x6
- ; CHECK: renamable $x6 = ADDI8 renamable $x5, 2
- ; CHECK: $x3 = ADD8 killed renamable $x5, $x6
- ; CHECK: $x3 = ADD8 $x3, killed renamable $x8
- ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
- renamable $x5 = COPY killed renamable $x7
- renamable $x6 = ADDI8 renamable $x4, 1
- renamable $x7 = COPY killed renamable $x6
- renamable $x8 = COPY killed renamable $x7
- renamable $x6 = ADDI8 renamable $x5, 2
- renamable $x7 = COPY killed renamable $x6
- $x3 = ADD8 renamable killed $x5, renamable killed $x7
- $x3 = ADD8 $x3, renamable killed $x8
- BLR8 implicit $lr8, implicit undef $rm, implicit $x3
-
-...
-
----
-name: bogus
-alignment: 4
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x7
- ; CHECK-LABEL: name: bogus
- ; CHECK: liveins: $x7
- ; CHECK: renamable $x5 = COPY renamable $x7
- ; CHECK: renamable $x6 = ADDI8 $x7, 1
- ; CHECK: renamable $x7 = COPY $x6
- ; CHECK: renamable $x6 = ADDI8 renamable $x5, 2
- ; CHECK: $x3 = ADD8 $x7, killed renamable $x5
- ; CHECK: $x3 = ADD8 $x3, killed renamable $x6
- ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
- renamable $x5 = COPY killed renamable $x7
- renamable $x6 = ADDI8 renamable $x5, 1
- renamable $x4 = COPY killed renamable $x6
- renamable $x7 = COPY killed renamable $x4
- renamable $x6 = ADDI8 renamable $x5, 2
- renamable $x4 = COPY killed renamable $x7
- $x3 = ADD8 renamable killed $x4, renamable killed $x5
- $x3 = ADD8 $x3, renamable killed $x6
- BLR8 implicit $lr8, implicit undef $rm, implicit $x3
-
-...
-
----
-name: foobar
-alignment: 4
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x7
- ; CHECK-LABEL: name: foobar
- ; CHECK: liveins: $x7
- ; CHECK: renamable $x6 = ADDI8 $x7, 1
- ; CHECK: renamable $x8 = COPY $x6
- ; CHECK: renamable $x6 = ADDI8 $x7, 2
- ; CHECK: $x3 = ADD8 $x6, $x7
- ; CHECK: $x3 = ADD8 $x3, killed renamable $x8
- ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
- renamable $x5 = COPY killed renamable $x7
- renamable $x6 = ADDI8 renamable $x5, 1
- renamable $x4 = COPY killed renamable $x6
- renamable $x8 = COPY killed renamable $x4
- renamable $x6 = ADDI8 renamable $x5, 2
- renamable $x4 = COPY killed renamable $x6
- $x3 = ADD8 renamable killed $x4, renamable killed $x5
- $x3 = ADD8 $x3, renamable killed $x8
- BLR8 implicit $lr8, implicit undef $rm, implicit $x3
-
-...
Removed: llvm/trunk/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir?rev=371856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir (removed)
@@ -1,67 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O3 -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 -run-pass=ppc-mi-peepholes \
-# RUN: -simplify-mir %s -o - | FileCheck %s
----
-name: poc
-alignment: 16
-tracksRegLiveness: true
-body: |
- ; CHECK-LABEL: name: poc
- ; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1, %bb.2
- ; CHECK: liveins: $x3, $x4, $x5, $x6
- ; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x6
- ; CHECK: [[COPY1:%[0-9]+]]:g8rc = COPY $x5
- ; CHECK: [[COPY2:%[0-9]+]]:g8rc = COPY $x4
- ; CHECK: [[COPY3:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
- ; CHECK: [[ANDIo8_:%[0-9]+]]:g8rc = ANDIo8 [[COPY1]], 1, implicit-def $cr0
- ; CHECK: [[COPY4:%[0-9]+]]:crbitrc = COPY $cr0gt
- ; CHECK: BCn killed [[COPY4]], %bb.2
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: liveins: $x3
- ; CHECK: [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
- ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDIo8_]], 2, 61
- ; CHECK: $x3 = COPY [[RLDICR]]
- ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
- ; CHECK: [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
- ; CHECK: $x3 = COPY [[ADD8_]]
- ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
- ; CHECK: bb.2:
- ; CHECK: [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
- ; CHECK: [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
- ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], [[COPY5]], %subreg.sub_32
- ; CHECK: $x3 = COPY [[INSERT_SUBREG]]
- ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
- bb.0.entry:
- successors: %bb.1, %bb.2
- liveins: $x3, $x4, $x5, $x6
-
- %4:g8rc = COPY $x6
- %3:g8rc = COPY $x5
- %2:g8rc = COPY $x4
- %1:g8rc_and_g8rc_nox0 = COPY $x3
- %11:g8rc = ANDIo8 %3, 1, implicit-def $cr0
- %6:crbitrc = COPY $cr0gt
- BCn killed %6, %bb.2
- B %bb.1
-
- bb.1:
- liveins: $x3
-
- %0:g8rc = EXTSW $x3
- %12:g8rc = RLDICR %11, 2, 61
- $x3 = COPY %12:g8rc
- %9:g8rc = RLDICR %0, 2, 61
- %10:g8rc = ADD8 %1, %9
- $x3 = COPY %10
- BLR8 implicit $lr8, implicit $rm, implicit $x3
-
- bb.2:
- %5:gprc = COPY %4.sub_32
- %8:g8rc = IMPLICIT_DEF
- %7:g8rc = INSERT_SUBREG %8, %5, %subreg.sub_32
- $x3 = COPY %7
- BLR8 implicit $lr8, implicit $rm, implicit $x3
-
-...
Removed: llvm/trunk/test/CodeGen/MIR/PowerPC/prolog_vec_spills.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/PowerPC/prolog_vec_spills.mir?rev=371856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/PowerPC/prolog_vec_spills.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/PowerPC/prolog_vec_spills.mir (removed)
@@ -1,62 +0,0 @@
-# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -run-pass=prologepilog -ppc-enable-pe-vector-spills %s -o - | FileCheck %s
-
----
-name: test1BB
-alignment: 16
-tracksRegLiveness: true
-liveins:
-body: |
- bb.0.entry:
- $r14 = IMPLICIT_DEF
- $r15 = IMPLICIT_DEF
- $r16 = IMPLICIT_DEF
- $f0 = IMPLICIT_DEF
- $v20 = IMPLICIT_DEF
- BLR8 implicit undef $lr8, implicit undef $rm
-
-# CHECK-LABEL: name: test1BB
-# CHECK: body: |
-# CHECK: $f1 = MTVSRD killed $x14
-# CHECK-NEXT: $f2 = MTVSRD killed $x15
-# CHECK-NEXT: $f3 = MTVSRD killed $x16
-# CHECK: $x16 = MFVSRD killed $f3
-# CHECK-NEXT: $x15 = MFVSRD killed $f2
-# CHECK-NEXT: $x14 = MFVSRD killed $f1
-...
-
----
-name: test2BBs
-alignment: 16
-tracksRegLiveness: true
-liveins:
-body: |
- bb.0.entry:
- successors: %bb.1, %bb.2
-
- $cr0 = IMPLICIT_DEF
- BCC 4, killed renamable $cr0, %bb.2
- B %bb.1
-
- bb.1:
- $r14 = IMPLICIT_DEF
- $r15 = IMPLICIT_DEF
- $r16 = IMPLICIT_DEF
- $r3 = IMPLICIT_DEF
- B %bb.3
-
- bb.2:
- liveins: $x3
- $r3 = IMPLICIT_DEF
-
- bb.3:
- BLR8 implicit undef $lr8, implicit undef $rm
-
-# CHECK-LABEL: name: test2BB
-# CHECK: body: |
-# CHECK: $f0 = MTVSRD killed $x14
-# CHECK-NEXT: $f1 = MTVSRD killed $x15
-# CHECK-NEXT: $f2 = MTVSRD killed $x16
-# CHECK: $x16 = MFVSRD killed $f2
-# CHECK-NEXT: $x15 = MFVSRD killed $f1
-# CHECK-NEXT: $x14 = MFVSRD killed $f0
-...
Added: llvm/trunk/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir?rev=371857&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir (added)
+++ llvm/trunk/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir Fri Sep 13 07:18:36 2019
@@ -0,0 +1,34 @@
+# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -run-pass=if-converter %s -o - | FileCheck %s
+---
+name: foo
+body: |
+ bb.0:
+ liveins: $x0, $x3
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+
+ dead renamable $x3 = ANDIo8 killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+ $cr2lt = CROR $cr0gt, $cr0gt
+ BCn killed renamable $cr2lt, %bb.2
+ B %bb.1
+
+ bb.1:
+ renamable $x3 = LIS8 4096
+ MTLR8 $x0, implicit-def $lr8
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+ bb.2:
+ renamable $x3 = LIS8 4096
+ MTLR8 $x0, implicit-def $lr8
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
+...
+
+# Diamond testcase with equivalent branches terminating in returns.
+
+# CHECK: body: |
+# CHECK: bb.0:
+# CHECK: dead renamable $x3 = ANDIo8 killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+# CHECK: $cr2lt = CROR $cr0gt, $cr0gt
+# CHECK: renamable $x3 = LIS8 4096
+# CHECK: MTLR8 $x0, implicit-def $lr8
+# CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
+
Added: llvm/trunk/test/CodeGen/PowerPC/machine-backward-cp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/machine-backward-cp.mir?rev=371857&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/machine-backward-cp.mir (added)
+++ llvm/trunk/test/CodeGen/PowerPC/machine-backward-cp.mir Fri Sep 13 07:18:36 2019
@@ -0,0 +1,281 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O3 -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+# RUN: -mcpu=pwr9 -simplify-mir -run-pass=machine-cp %s -o - | FileCheck %s
+
+# Normal case
+---
+name: test0
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test0
+ ; CHECK: renamable $x4 = LI8 1024
+ ; CHECK: $x3 = COPY killed renamable $x4
+ ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+ renamable $x4 = LI8 1024
+ $x3 = COPY renamable killed $x4
+ BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+
+...
+
+# Not in terminal BBs
+---
+name: test1
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test1
+ ; CHECK: bb.0.entry:
+ ; CHECK: renamable $x5 = LI8 42
+ ; CHECK: renamable $x4 = COPY killed renamable $x5
+ ; CHECK: B %bb.1
+ ; CHECK: bb.1:
+ ; CHECK: liveins: $x4
+ ; CHECK: $x3 = COPY killed renamable $x4
+ ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+ bb.0.entry:
+ successors: %bb.1
+
+ renamable $x5 = LI8 42
+ renamable $x4 = COPY renamable killed $x5
+ B %bb.1
+
+ bb.1:
+ liveins: $x4
+ $x3 = COPY renamable killed $x4
+ BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+
+...
+
+# Use reserved register
+---
+name: test2
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test2
+ ; CHECK: renamable $x4 = LI8 1024
+ ; CHECK: $x13 = COPY killed renamable $x4
+ ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit undef $x3
+ renamable $x4 = LI8 1024
+ $x13 = COPY renamable killed $x4
+ BLR8 implicit $lr8, implicit undef $rm, implicit undef $x3
+
+...
+
+# Intermediate read of copy's src
+---
+name: test3
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test3
+ ; CHECK: renamable $x4 = LI8 0
+ ; CHECK: renamable $x5 = ADDI8 $x4, 1
+ ; CHECK: $x3 = COPY killed renamable $x4
+ ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+ renamable $x4 = LI8 0
+ renamable $x5 = ADDI8 $x4, 1
+ $x3 = COPY renamable killed $x4
+ BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+
+...
+
+# Intermediate read of copy's def
+---
+name: test4
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x3
+
+ ; CHECK-LABEL: name: test4
+ ; CHECK: liveins: $x3
+ ; CHECK: renamable $x4 = LI8 0
+ ; CHECK: renamable $x5 = ADDI8 $x3, 1
+ ; CHECK: $x3 = COPY killed renamable $x4
+ ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+ renamable $x4 = LI8 0
+ renamable $x5 = ADDI8 $x3, 1
+ $x3 = COPY renamable killed $x4
+ BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+
+...
+
+# Intermiediate clobber of copy's def
+---
+name: test5
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x3, $x5
+
+ ; CHECK-LABEL: name: test5
+ ; CHECK: liveins: $x3, $x5
+ ; CHECK: renamable $x4 = LI8 0
+ ; CHECK: renamable $x3 = ADDI8 $x5, 1
+ ; CHECK: $x3 = COPY killed renamable $x4
+ ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+ renamable $x4 = LI8 0
+ renamable $x3 = ADDI8 $x5, 1
+ $x3 = COPY renamable killed $x4
+ BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+
+...
+
+---
+name: iterative_deletion
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x5
+
+ ; CHECK-LABEL: name: iterative_deletion
+ ; CHECK: liveins: $x5
+ ; CHECK: renamable $x6 = ADDI8 killed renamable $x5, 1
+ ; CHECK: $x3 = COPY $x6
+ ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+ renamable $x6 = ADDI8 renamable killed $x5, 1
+ renamable $x4 = COPY renamable killed $x6
+ renamable $x7 = COPY renamable killed $x4
+ $x3 = COPY renamable killed $x7
+ BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+
+...
+
+---
+name: Enter
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x4, $x7
+ ; CHECK-LABEL: name: Enter
+ ; CHECK: liveins: $x4, $x7
+ ; CHECK: renamable $x5 = COPY killed renamable $x7
+ ; CHECK: renamable $x6 = ADDI8 killed renamable $x4, 1
+ ; CHECK: $x3 = ADD8 killed renamable $x5, $x6
+ ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+ renamable $x5 = COPY killed renamable $x7
+ renamable $x6 = ADDI8 killed renamable $x4, 1
+ renamable $x7 = COPY killed renamable $x6
+ $x3 = ADD8 renamable killed $x5, renamable killed $x7
+ BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+
+...
+
+---
+name: foo
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x4, $x7
+ ; CHECK-LABEL: name: foo
+ ; CHECK: liveins: $x4, $x7
+ ; CHECK: renamable $x5 = COPY killed renamable $x7
+ ; CHECK: renamable $x6 = ADDI8 renamable $x4, 1
+ ; CHECK: renamable $x7 = COPY killed renamable $x6
+ ; CHECK: renamable $x8 = ADDI8 killed $x4, 2
+ ; CHECK: $x3 = ADD8 killed renamable $x5, $x8
+ ; CHECK: $x3 = ADD8 $x3, killed renamable $x7
+ ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+ renamable $x5 = COPY killed renamable $x7
+ renamable $x6 = ADDI8 renamable $x4, 1
+ renamable $x7 = COPY killed renamable $x6
+ renamable $x8 = ADDI8 killed $x4, 2
+ renamable $x6 = COPY killed renamable $x8
+ $x3 = ADD8 renamable killed $x5, renamable killed $x6
+ $x3 = ADD8 $x3, renamable killed $x7
+ BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+
+...
+
+---
+name: bar
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x4, $x7
+ ; CHECK-LABEL: name: bar
+ ; CHECK: liveins: $x4, $x7
+ ; CHECK: renamable $x5 = COPY killed renamable $x7
+ ; CHECK: renamable $x6 = ADDI8 renamable $x4, 1
+ ; CHECK: renamable $x8 = COPY $x6
+ ; CHECK: renamable $x6 = ADDI8 renamable $x5, 2
+ ; CHECK: $x3 = ADD8 killed renamable $x5, $x6
+ ; CHECK: $x3 = ADD8 $x3, killed renamable $x8
+ ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+ renamable $x5 = COPY killed renamable $x7
+ renamable $x6 = ADDI8 renamable $x4, 1
+ renamable $x7 = COPY killed renamable $x6
+ renamable $x8 = COPY killed renamable $x7
+ renamable $x6 = ADDI8 renamable $x5, 2
+ renamable $x7 = COPY killed renamable $x6
+ $x3 = ADD8 renamable killed $x5, renamable killed $x7
+ $x3 = ADD8 $x3, renamable killed $x8
+ BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+
+...
+
+---
+name: bogus
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x7
+ ; CHECK-LABEL: name: bogus
+ ; CHECK: liveins: $x7
+ ; CHECK: renamable $x5 = COPY renamable $x7
+ ; CHECK: renamable $x6 = ADDI8 $x7, 1
+ ; CHECK: renamable $x7 = COPY $x6
+ ; CHECK: renamable $x6 = ADDI8 renamable $x5, 2
+ ; CHECK: $x3 = ADD8 $x7, killed renamable $x5
+ ; CHECK: $x3 = ADD8 $x3, killed renamable $x6
+ ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+ renamable $x5 = COPY killed renamable $x7
+ renamable $x6 = ADDI8 renamable $x5, 1
+ renamable $x4 = COPY killed renamable $x6
+ renamable $x7 = COPY killed renamable $x4
+ renamable $x6 = ADDI8 renamable $x5, 2
+ renamable $x4 = COPY killed renamable $x7
+ $x3 = ADD8 renamable killed $x4, renamable killed $x5
+ $x3 = ADD8 $x3, renamable killed $x6
+ BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+
+...
+
+---
+name: foobar
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x7
+ ; CHECK-LABEL: name: foobar
+ ; CHECK: liveins: $x7
+ ; CHECK: renamable $x6 = ADDI8 $x7, 1
+ ; CHECK: renamable $x8 = COPY $x6
+ ; CHECK: renamable $x6 = ADDI8 $x7, 2
+ ; CHECK: $x3 = ADD8 $x6, $x7
+ ; CHECK: $x3 = ADD8 $x3, killed renamable $x8
+ ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+ renamable $x5 = COPY killed renamable $x7
+ renamable $x6 = ADDI8 renamable $x5, 1
+ renamable $x4 = COPY killed renamable $x6
+ renamable $x8 = COPY killed renamable $x4
+ renamable $x6 = ADDI8 renamable $x5, 2
+ renamable $x4 = COPY killed renamable $x6
+ $x3 = ADD8 renamable killed $x4, renamable killed $x5
+ $x3 = ADD8 $x3, renamable killed $x8
+ BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+
+...
Added: llvm/trunk/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir?rev=371857&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir (added)
+++ llvm/trunk/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir Fri Sep 13 07:18:36 2019
@@ -0,0 +1,67 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O3 -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 -run-pass=ppc-mi-peepholes \
+# RUN: -simplify-mir %s -o - | FileCheck %s
+---
+name: poc
+alignment: 16
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: poc
+ ; CHECK: bb.0.entry:
+ ; CHECK: successors: %bb.1, %bb.2
+ ; CHECK: liveins: $x3, $x4, $x5, $x6
+ ; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x6
+ ; CHECK: [[COPY1:%[0-9]+]]:g8rc = COPY $x5
+ ; CHECK: [[COPY2:%[0-9]+]]:g8rc = COPY $x4
+ ; CHECK: [[COPY3:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
+ ; CHECK: [[ANDIo8_:%[0-9]+]]:g8rc = ANDIo8 [[COPY1]], 1, implicit-def $cr0
+ ; CHECK: [[COPY4:%[0-9]+]]:crbitrc = COPY $cr0gt
+ ; CHECK: BCn killed [[COPY4]], %bb.2
+ ; CHECK: B %bb.1
+ ; CHECK: bb.1:
+ ; CHECK: liveins: $x3
+ ; CHECK: [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
+ ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDIo8_]], 2, 61
+ ; CHECK: $x3 = COPY [[RLDICR]]
+ ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
+ ; CHECK: [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
+ ; CHECK: $x3 = COPY [[ADD8_]]
+ ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ; CHECK: bb.2:
+ ; CHECK: [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
+ ; CHECK: [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], [[COPY5]], %subreg.sub_32
+ ; CHECK: $x3 = COPY [[INSERT_SUBREG]]
+ ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ bb.0.entry:
+ successors: %bb.1, %bb.2
+ liveins: $x3, $x4, $x5, $x6
+
+ %4:g8rc = COPY $x6
+ %3:g8rc = COPY $x5
+ %2:g8rc = COPY $x4
+ %1:g8rc_and_g8rc_nox0 = COPY $x3
+ %11:g8rc = ANDIo8 %3, 1, implicit-def $cr0
+ %6:crbitrc = COPY $cr0gt
+ BCn killed %6, %bb.2
+ B %bb.1
+
+ bb.1:
+ liveins: $x3
+
+ %0:g8rc = EXTSW $x3
+ %12:g8rc = RLDICR %11, 2, 61
+ $x3 = COPY %12:g8rc
+ %9:g8rc = RLDICR %0, 2, 61
+ %10:g8rc = ADD8 %1, %9
+ $x3 = COPY %10
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+ bb.2:
+ %5:gprc = COPY %4.sub_32
+ %8:g8rc = IMPLICIT_DEF
+ %7:g8rc = INSERT_SUBREG %8, %5, %subreg.sub_32
+ $x3 = COPY %7
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+...
Added: llvm/trunk/test/CodeGen/PowerPC/prolog_vec_spills.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/prolog_vec_spills.mir?rev=371857&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/prolog_vec_spills.mir (added)
+++ llvm/trunk/test/CodeGen/PowerPC/prolog_vec_spills.mir Fri Sep 13 07:18:36 2019
@@ -0,0 +1,62 @@
+# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -run-pass=prologepilog -ppc-enable-pe-vector-spills %s -o - | FileCheck %s
+
+---
+name: test1BB
+alignment: 16
+tracksRegLiveness: true
+liveins:
+body: |
+ bb.0.entry:
+ $r14 = IMPLICIT_DEF
+ $r15 = IMPLICIT_DEF
+ $r16 = IMPLICIT_DEF
+ $f0 = IMPLICIT_DEF
+ $v20 = IMPLICIT_DEF
+ BLR8 implicit undef $lr8, implicit undef $rm
+
+# CHECK-LABEL: name: test1BB
+# CHECK: body: |
+# CHECK: $f1 = MTVSRD killed $x14
+# CHECK-NEXT: $f2 = MTVSRD killed $x15
+# CHECK-NEXT: $f3 = MTVSRD killed $x16
+# CHECK: $x16 = MFVSRD killed $f3
+# CHECK-NEXT: $x15 = MFVSRD killed $f2
+# CHECK-NEXT: $x14 = MFVSRD killed $f1
+...
+
+---
+name: test2BBs
+alignment: 16
+tracksRegLiveness: true
+liveins:
+body: |
+ bb.0.entry:
+ successors: %bb.1, %bb.2
+
+ $cr0 = IMPLICIT_DEF
+ BCC 4, killed renamable $cr0, %bb.2
+ B %bb.1
+
+ bb.1:
+ $r14 = IMPLICIT_DEF
+ $r15 = IMPLICIT_DEF
+ $r16 = IMPLICIT_DEF
+ $r3 = IMPLICIT_DEF
+ B %bb.3
+
+ bb.2:
+ liveins: $x3
+ $r3 = IMPLICIT_DEF
+
+ bb.3:
+ BLR8 implicit undef $lr8, implicit undef $rm
+
+# CHECK-LABEL: name: test2BB
+# CHECK: body: |
+# CHECK: $f0 = MTVSRD killed $x14
+# CHECK-NEXT: $f1 = MTVSRD killed $x15
+# CHECK-NEXT: $f2 = MTVSRD killed $x16
+# CHECK: $x16 = MFVSRD killed $f2
+# CHECK-NEXT: $x15 = MFVSRD killed $f1
+# CHECK-NEXT: $x14 = MFVSRD killed $f0
+...
More information about the llvm-commits
mailing list