[llvm] r371807 - AMDGPU/GlobalISel: Select 16-bit VALU bit ops
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 12 20:55:43 PDT 2019
Author: arsenm
Date: Thu Sep 12 20:55:43 2019
New Revision: 371807
URL: http://llvm.org/viewvc/llvm-project?rev=371807&view=rev
Log:
AMDGPU/GlobalISel: Select 16-bit VALU bit ops
Modified:
llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
Modified: llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td?rev=371807&r1=371806&r2=371807&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td Thu Sep 12 20:55:43 2019
@@ -798,17 +798,17 @@ defm : Arithmetic_i16_Pats<umax, V_MAX_U
def : GCNPat <
(and i16:$src0, i16:$src1),
- (V_AND_B32_e64 $src0, $src1)
+ (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
>;
def : GCNPat <
(or i16:$src0, i16:$src1),
- (V_OR_B32_e64 $src0, $src1)
+ (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
>;
def : GCNPat <
(xor i16:$src0, i16:$src1),
- (V_XOR_B32_e64 $src0, $src1)
+ (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
>;
let Predicates = [Has16BitInsts, isGFX7GFX8GFX9] in {
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir?rev=371807&r1=371806&r2=371807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir Thu Sep 12 20:55:43 2019
@@ -156,12 +156,11 @@ body: |
; WAVE64: S_ENDPGM 0, implicit [[AND]](s16)
; WAVE32-LABEL: name: and_s16_vgpr_vgpr_vgpr
; WAVE32: liveins: $vgpr0, $vgpr1
- ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; WAVE32: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
- ; WAVE32: [[AND:%[0-9]+]]:vgpr(s16) = G_AND [[TRUNC]], [[TRUNC1]]
- ; WAVE32: S_ENDPGM 0, implicit [[AND]](s16)
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir?rev=371807&r1=371806&r2=371807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir Thu Sep 12 20:55:43 2019
@@ -156,12 +156,11 @@ body: |
; WAVE64: S_ENDPGM 0, implicit [[OR]](s16)
; WAVE32-LABEL: name: or_s16_vgpr_vgpr_vgpr
; WAVE32: liveins: $vgpr0, $vgpr1
- ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; WAVE32: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
- ; WAVE32: [[OR:%[0-9]+]]:vgpr(s16) = G_OR [[TRUNC]], [[TRUNC1]]
- ; WAVE32: S_ENDPGM 0, implicit [[OR]](s16)
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir?rev=371807&r1=371806&r2=371807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir Thu Sep 12 20:55:43 2019
@@ -156,12 +156,11 @@ body: |
; WAVE64: S_ENDPGM 0, implicit [[XOR]](s16)
; WAVE32-LABEL: name: xor_s16_vgpr_vgpr_vgpr
; WAVE32: liveins: $vgpr0, $vgpr1
- ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; WAVE32: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
- ; WAVE32: [[XOR:%[0-9]+]]:vgpr(s16) = G_XOR [[TRUNC]], [[TRUNC1]]
- ; WAVE32: S_ENDPGM 0, implicit [[XOR]](s16)
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0
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