[llvm] r371779 - [PowerPC] Remove the SPE4RC register class and instead add f32 to the GPRC register class.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 12 15:07:36 PDT 2019
Author: ctopper
Date: Thu Sep 12 15:07:35 2019
New Revision: 371779
URL: http://llvm.org/viewvc/llvm-project?rev=371779&view=rev
Log:
[PowerPC] Remove the SPE4RC register class and instead add f32 to the GPRC register class.
Summary:
Since the SPE4RC register class contains an identical set of registers
and an identical spill size to the GPRC class its slightly confusing
the tablegen emitter. It's preventing the GPRC_and_GPRC_NOR0 synthesized
register class from inheriting VTs and AltOrders from GPRC or GPRC_NOR0.
This is because SPE4C is found first in the super register class list
when inheriting these properties and it doesn't set the VTs or
AltOrders the same way as GPRC or GPRC_NOR0.
This patch replaces all uses of GPE4RC with GPRC and allows GPRC and
GPRC_NOR0 to contain f32.
The test changes here are because the AltOrders are being inherited
to GPRC_NOR0 now.
Found while trying to determine if getCommonSubClass needs to take
a VT argument. It was originally added to support fp128 on x86-64,
I've changed some things about that so that it might be needed
anymore. But a PowerPC test crashed without it and I think its
due to this subclass issue.
Reviewers: jhibbits, nemanjai, kbarton, hfinkel
Subscribers: wuzish, nemanjai, mehdi_amini, hiraditya, kbarton, MaskRay, dexonsmith, jsji, shchenz, steven.zhang, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67513
Modified:
llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/trunk/test/CodeGen/PowerPC/inc-of-add.ll
llvm/trunk/test/CodeGen/PowerPC/sub-of-not.ll
Modified: llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp?rev=371779&r1=371778&r2=371779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp Thu Sep 12 15:07:35 2019
@@ -167,12 +167,6 @@ static DecodeStatus DecodeQFRCRegisterCl
return decodeRegisterClass(Inst, RegNo, QFRegs);
}
-static DecodeStatus DecodeSPE4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
- uint64_t Address,
- const void *Decoder) {
- return decodeRegisterClass(Inst, RegNo, RRegs);
-}
-
static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
Modified: llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp?rev=371779&r1=371778&r2=371779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp Thu Sep 12 15:07:35 2019
@@ -469,7 +469,7 @@ bool PPCFastISel::PPCEmitLoad(MVT VT, Re
(ResultReg ? MRI.getRegClass(ResultReg) :
(RC ? RC :
(VT == MVT::f64 ? (HasSPE ? &PPC::SPERCRegClass : &PPC::F8RCRegClass) :
- (VT == MVT::f32 ? (HasSPE ? &PPC::SPE4RCRegClass : &PPC::F4RCRegClass) :
+ (VT == MVT::f32 ? (HasSPE ? &PPC::GPRCRegClass : &PPC::F4RCRegClass) :
(VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
&PPC::GPRC_and_GPRC_NOR0RegClass)))));
@@ -989,7 +989,7 @@ bool PPCFastISel::SelectFPTrunc(const In
unsigned DestReg;
auto RC = MRI.getRegClass(SrcReg);
if (PPCSubTarget->hasSPE()) {
- DestReg = createResultReg(&PPC::SPE4RCRegClass);
+ DestReg = createResultReg(&PPC::GPRCRegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::EFSCFD), DestReg)
.addReg(SrcReg);
@@ -1229,9 +1229,9 @@ bool PPCFastISel::SelectFPToI(const Inst
if (PPCSubTarget->hasSPE()) {
DestReg = createResultReg(&PPC::GPRCRegClass);
if (IsSigned)
- Opc = InRC == &PPC::SPE4RCRegClass ? PPC::EFSCTSIZ : PPC::EFDCTSIZ;
+ Opc = InRC == &PPC::GPRCRegClass ? PPC::EFSCTSIZ : PPC::EFDCTSIZ;
else
- Opc = InRC == &PPC::SPE4RCRegClass ? PPC::EFSCTUIZ : PPC::EFDCTUIZ;
+ Opc = InRC == &PPC::GPRCRegClass ? PPC::EFSCTUIZ : PPC::EFDCTUIZ;
} else if (isVSFRCRegClass(RC)) {
DestReg = createResultReg(&PPC::VSFRCRegClass);
if (DstVT == MVT::i32)
@@ -2002,7 +2002,7 @@ unsigned PPCFastISel::PPCMaterializeFP(c
const bool HasSPE = PPCSubTarget->hasSPE();
const TargetRegisterClass *RC;
if (HasSPE)
- RC = ((VT == MVT::f32) ? &PPC::SPE4RCRegClass : &PPC::SPERCRegClass);
+ RC = ((VT == MVT::f32) ? &PPC::GPRCRegClass : &PPC::SPERCRegClass);
else
RC = ((VT == MVT::f32) ? &PPC::F4RCRegClass : &PPC::F8RCRegClass);
Modified: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=371779&r1=371778&r2=371779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp Thu Sep 12 15:07:35 2019
@@ -1886,8 +1886,7 @@ void PPCFrameLowering::processFunctionBe
assert((!MF.getInfo<PPCFunctionInfo>()->mustSaveTOC() ||
(Reg != PPC::X2 && Reg != PPC::R2)) &&
"Not expecting to try to spill R2 in a function that must save TOC");
- if (PPC::GPRCRegClass.contains(Reg) ||
- PPC::SPE4RCRegClass.contains(Reg)) {
+ if (PPC::GPRCRegClass.contains(Reg)) {
HasGPSaveArea = true;
GPRegs.push_back(CSI[i]);
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=371779&r1=371778&r2=371779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Sep 12 15:07:35 2019
@@ -145,7 +145,7 @@ PPCTargetLowering::PPCTargetLowering(con
addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
if (!useSoftFloat()) {
if (hasSPE()) {
- addRegisterClass(MVT::f32, &PPC::SPE4RCRegClass);
+ addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
} else {
addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
@@ -3482,7 +3482,7 @@ SDValue PPCTargetLowering::LowerFormalAr
if (Subtarget.hasP8Vector())
RC = &PPC::VSSRCRegClass;
else if (Subtarget.hasSPE())
- RC = &PPC::SPE4RCRegClass;
+ RC = &PPC::GPRCRegClass;
else
RC = &PPC::F4RCRegClass;
break;
@@ -14166,7 +14166,7 @@ PPCTargetLowering::getRegForInlineAsmCon
case 'f':
if (Subtarget.hasSPE()) {
if (VT == MVT::f32 || VT == MVT::i32)
- return std::make_pair(0U, &PPC::SPE4RCRegClass);
+ return std::make_pair(0U, &PPC::GPRCRegClass);
if (VT == MVT::f64 || VT == MVT::i64)
return std::make_pair(0U, &PPC::SPERCRegClass);
} else {
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=371779&r1=371778&r2=371779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Thu Sep 12 15:07:35 2019
@@ -90,7 +90,6 @@ enum SpillOpcodeKey {
SOK_QuadBitSpill,
SOK_SpillToVSR,
SOK_SPESpill,
- SOK_SPE4Spill,
SOK_LastOpcodeSpill // This must be last on the enum.
};
@@ -967,11 +966,11 @@ void PPCInstrInfo::copyPhysReg(MachineBa
getKillRegState(KillSrc);
return;
} else if (PPC::SPERCRegClass.contains(SrcReg) &&
- PPC::SPE4RCRegClass.contains(DestReg)) {
+ PPC::GPRCRegClass.contains(DestReg)) {
BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
getKillRegState(KillSrc);
return;
- } else if (PPC::SPE4RCRegClass.contains(SrcReg) &&
+ } else if (PPC::GPRCRegClass.contains(SrcReg) &&
PPC::SPERCRegClass.contains(DestReg)) {
BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
getKillRegState(KillSrc);
@@ -1010,8 +1009,6 @@ void PPCInstrInfo::copyPhysReg(MachineBa
Opc = PPC::QVFMRb;
else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
Opc = PPC::CROR;
- else if (PPC::SPE4RCRegClass.contains(DestReg, SrcReg))
- Opc = PPC::OR;
else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
Opc = PPC::EVOR;
else
@@ -1044,8 +1041,6 @@ unsigned PPCInstrInfo::getStoreOpcodeFor
OpcodeIndex = SOK_Float4Spill;
} else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_SPESpill;
- } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
- OpcodeIndex = SOK_SPE4Spill;
} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_CRSpill;
} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
@@ -1084,8 +1079,6 @@ unsigned PPCInstrInfo::getStoreOpcodeFor
OpcodeIndex = SOK_Float4Spill;
} else if (PPC::SPERCRegClass.contains(Reg)) {
OpcodeIndex = SOK_SPESpill;
- } else if (PPC::SPE4RCRegClass.contains(Reg)) {
- OpcodeIndex = SOK_SPE4Spill;
} else if (PPC::CRRCRegClass.contains(Reg)) {
OpcodeIndex = SOK_CRSpill;
} else if (PPC::CRBITRCRegClass.contains(Reg)) {
@@ -1134,8 +1127,6 @@ PPCInstrInfo::getLoadOpcodeForSpill(unsi
OpcodeIndex = SOK_Float4Spill;
} else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_SPESpill;
- } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
- OpcodeIndex = SOK_SPE4Spill;
} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
OpcodeIndex = SOK_CRSpill;
} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
@@ -1174,8 +1165,6 @@ PPCInstrInfo::getLoadOpcodeForSpill(unsi
OpcodeIndex = SOK_Float4Spill;
} else if (PPC::SPERCRegClass.contains(Reg)) {
OpcodeIndex = SOK_SPESpill;
- } else if (PPC::SPE4RCRegClass.contains(Reg)) {
- OpcodeIndex = SOK_SPE4Spill;
} else if (PPC::CRRCRegClass.contains(Reg)) {
OpcodeIndex = SOK_CRSpill;
} else if (PPC::CRBITRCRegClass.contains(Reg)) {
@@ -2433,7 +2422,7 @@ const unsigned *PPCInstrInfo::getStoreOp
{PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,
PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
- PPC::SPILLTOVSR_ST, PPC::EVSTDD, PPC::SPESTW},
+ PPC::SPILLTOVSR_ST, PPC::EVSTDD},
// Power 9
{PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
@@ -2449,7 +2438,7 @@ const unsigned *PPCInstrInfo::getLoadOpc
{PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
- PPC::SPILLTOVSR_LD, PPC::EVLDD, PPC::SPELWZ},
+ PPC::SPILLTOVSR_LD, PPC::EVLDD},
// Power 9
{PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32,
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=371779&r1=371778&r2=371779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Thu Sep 12 15:07:35 2019
@@ -579,7 +579,7 @@ def sperc : RegisterOperand<SPERC> {
def PPCRegSPE4RCAsmOperand : AsmOperandClass {
let Name = "RegSPE4RC"; let PredicateMethod = "isRegNumber";
}
-def spe4rc : RegisterOperand<SPE4RC> {
+def spe4rc : RegisterOperand<GPRC> {
let ParserMatchClass = PPCRegSPE4RCAsmOperand;
}
@@ -3188,21 +3188,21 @@ def : Pat<(srl i32:$rS, i32:$rB),
def : Pat<(shl i32:$rS, i32:$rB),
(SLW $rS, $rB)>;
-def : Pat<(zextloadi1 iaddr:$src),
+def : Pat<(i32 (zextloadi1 iaddr:$src)),
(LBZ iaddr:$src)>;
-def : Pat<(zextloadi1 xaddr:$src),
+def : Pat<(i32 (zextloadi1 xaddr:$src)),
(LBZX xaddr:$src)>;
-def : Pat<(extloadi1 iaddr:$src),
+def : Pat<(i32 (extloadi1 iaddr:$src)),
(LBZ iaddr:$src)>;
-def : Pat<(extloadi1 xaddr:$src),
+def : Pat<(i32 (extloadi1 xaddr:$src)),
(LBZX xaddr:$src)>;
-def : Pat<(extloadi8 iaddr:$src),
+def : Pat<(i32 (extloadi8 iaddr:$src)),
(LBZ iaddr:$src)>;
-def : Pat<(extloadi8 xaddr:$src),
+def : Pat<(i32 (extloadi8 xaddr:$src)),
(LBZX xaddr:$src)>;
-def : Pat<(extloadi16 iaddr:$src),
+def : Pat<(i32 (extloadi16 iaddr:$src)),
(LHZ iaddr:$src)>;
-def : Pat<(extloadi16 xaddr:$src),
+def : Pat<(i32 (extloadi16 xaddr:$src)),
(LHZX xaddr:$src)>;
let Predicates = [HasFPU] in {
def : Pat<(f64 (extloadf32 iaddr:$src)),
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=371779&r1=371778&r2=371779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Sep 12 15:07:35 2019
@@ -425,7 +425,6 @@ unsigned PPCRegisterInfo::getRegPressure
case PPC::G8RC_NOX0RegClassID:
case PPC::GPRC_NOR0RegClassID:
case PPC::SPERCRegClassID:
- case PPC::SPE4RCRegClassID:
case PPC::G8RCRegClassID:
case PPC::GPRCRegClassID: {
unsigned FP = TFI->hasFP(MF) ? 1 : 0;
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td?rev=371779&r1=371778&r2=371779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td Thu Sep 12 15:07:35 2019
@@ -253,9 +253,9 @@ def RM: PPCReg<"**ROUNDING MODE**">;
/// Register classes
// Allocate volatiles first
// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
-def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
- (sequence "R%u", 30, 13),
- R31, R0, R1, FP, BP)> {
+def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12),
+ (sequence "R%u", 30, 13),
+ R31, R0, R1, FP, BP)> {
// On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
// put it at the end of the list.
let AltOrders = [(add (sub GPRC, R2), R2)];
@@ -278,7 +278,7 @@ def G8RC : RegisterClass<"PPC", [i64], 6
// For some instructions r0 is special (representing the value 0 instead of
// the value in the r0 register), and we use these register subclasses to
// prevent r0 from being allocated for use by those instructions.
-def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)> {
+def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)> {
// On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
// put it at the end of the list.
let AltOrders = [(add (sub GPRC_NOR0, R2), R2)];
@@ -300,8 +300,6 @@ def SPERC : RegisterClass<"PPC", [f64],
(sequence "S%u", 30, 13),
S31, S0, S1)>;
-def SPE4RC : RegisterClass<"PPC", [f32], 32, (add GPRC)>;
-
// Allocate volatiles first, then non-volatiles in reverse order. With the SVR4
// ABI the size of the Floating-point register save area is determined by the
// allocated non-volatile register with the lowest register number, as FP
Modified: llvm/trunk/test/CodeGen/PowerPC/inc-of-add.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/inc-of-add.ll?rev=371779&r1=371778&r2=371779&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/inc-of-add.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/inc-of-add.ll Thu Sep 12 15:07:35 2019
@@ -170,7 +170,6 @@ define <16 x i8> @vector_i128_i8(<16 x i
; PPC64BE-NEXT: std 23, -72(1) # 8-byte Folded Spill
; PPC64BE-NEXT: std 22, -80(1) # 8-byte Folded Spill
; PPC64BE-NEXT: std 26, -48(1) # 8-byte Folded Spill
-; PPC64BE-NEXT: std 2, -96(1) # 8-byte Folded Spill
; PPC64BE-NEXT: std 25, -56(1) # 8-byte Folded Spill
; PPC64BE-NEXT: std 24, -64(1) # 8-byte Folded Spill
; PPC64BE-NEXT: std 29, -24(1) # 8-byte Folded Spill
@@ -191,8 +190,8 @@ define <16 x i8> @vector_i128_i8(<16 x i
; PPC64BE-NEXT: add 7, 12, 7
; PPC64BE-NEXT: lbz 12, 239(1)
; PPC64BE-NEXT: lbz 26, 151(1)
-; PPC64BE-NEXT: add 2, 21, 23
-; PPC64BE-NEXT: lbz 23, 279(1)
+; PPC64BE-NEXT: add 23, 21, 23
+; PPC64BE-NEXT: lbz 21, 279(1)
; PPC64BE-NEXT: lbz 25, 143(1)
; PPC64BE-NEXT: add 11, 11, 22
; PPC64BE-NEXT: lbz 22, 271(1)
@@ -201,8 +200,8 @@ define <16 x i8> @vector_i128_i8(<16 x i
; PPC64BE-NEXT: lbz 12, 263(1)
; PPC64BE-NEXT: lbz 30, 175(1)
; PPC64BE-NEXT: lbz 29, 303(1)
-; PPC64BE-NEXT: add 26, 23, 26
-; PPC64BE-NEXT: lbz 23, 311(1)
+; PPC64BE-NEXT: add 26, 21, 26
+; PPC64BE-NEXT: lbz 21, 311(1)
; PPC64BE-NEXT: std 28, -32(1) # 8-byte Folded Spill
; PPC64BE-NEXT: add 25, 22, 25
; PPC64BE-NEXT: lbz 28, 167(1)
@@ -212,7 +211,7 @@ define <16 x i8> @vector_i128_i8(<16 x i
; PPC64BE-NEXT: lbz 27, 159(1)
; PPC64BE-NEXT: lbz 24, 287(1)
; PPC64BE-NEXT: add 30, 29, 30
-; PPC64BE-NEXT: add 29, 23, 0
+; PPC64BE-NEXT: add 29, 21, 0
; PPC64BE-NEXT: addi 0, 29, 1
; PPC64BE-NEXT: add 28, 22, 28
; PPC64BE-NEXT: stb 0, 15(3)
@@ -228,7 +227,7 @@ define <16 x i8> @vector_i128_i8(<16 x i
; PPC64BE-NEXT: stb 0, 11(3)
; PPC64BE-NEXT: addi 0, 25, 1
; PPC64BE-NEXT: stb 12, 9(3)
-; PPC64BE-NEXT: addi 12, 2, 1
+; PPC64BE-NEXT: addi 12, 23, 1
; PPC64BE-NEXT: addi 11, 11, 1
; PPC64BE-NEXT: addi 10, 10, 1
; PPC64BE-NEXT: addi 9, 9, 1
@@ -247,7 +246,6 @@ define <16 x i8> @vector_i128_i8(<16 x i
; PPC64BE-NEXT: stb 6, 2(3)
; PPC64BE-NEXT: stb 5, 1(3)
; PPC64BE-NEXT: stb 4, 0(3)
-; PPC64BE-NEXT: ld 2, -96(1) # 8-byte Folded Reload
; PPC64BE-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; PPC64BE-NEXT: ld 29, -24(1) # 8-byte Folded Reload
; PPC64BE-NEXT: ld 28, -32(1) # 8-byte Folded Reload
Modified: llvm/trunk/test/CodeGen/PowerPC/sub-of-not.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/sub-of-not.ll?rev=371779&r1=371778&r2=371779&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/sub-of-not.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/sub-of-not.ll Thu Sep 12 15:07:35 2019
@@ -170,7 +170,6 @@ define <16 x i8> @vector_i128_i8(<16 x i
; PPC64BE-NEXT: std 23, -72(1) # 8-byte Folded Spill
; PPC64BE-NEXT: std 22, -80(1) # 8-byte Folded Spill
; PPC64BE-NEXT: std 26, -48(1) # 8-byte Folded Spill
-; PPC64BE-NEXT: std 2, -96(1) # 8-byte Folded Spill
; PPC64BE-NEXT: std 25, -56(1) # 8-byte Folded Spill
; PPC64BE-NEXT: std 24, -64(1) # 8-byte Folded Spill
; PPC64BE-NEXT: std 29, -24(1) # 8-byte Folded Spill
@@ -191,8 +190,8 @@ define <16 x i8> @vector_i128_i8(<16 x i
; PPC64BE-NEXT: add 7, 12, 7
; PPC64BE-NEXT: lbz 12, 239(1)
; PPC64BE-NEXT: lbz 26, 151(1)
-; PPC64BE-NEXT: add 2, 21, 23
-; PPC64BE-NEXT: lbz 23, 279(1)
+; PPC64BE-NEXT: add 23, 21, 23
+; PPC64BE-NEXT: lbz 21, 279(1)
; PPC64BE-NEXT: lbz 25, 143(1)
; PPC64BE-NEXT: add 11, 11, 22
; PPC64BE-NEXT: lbz 22, 271(1)
@@ -201,8 +200,8 @@ define <16 x i8> @vector_i128_i8(<16 x i
; PPC64BE-NEXT: lbz 12, 263(1)
; PPC64BE-NEXT: lbz 30, 175(1)
; PPC64BE-NEXT: lbz 29, 303(1)
-; PPC64BE-NEXT: add 26, 23, 26
-; PPC64BE-NEXT: lbz 23, 311(1)
+; PPC64BE-NEXT: add 26, 21, 26
+; PPC64BE-NEXT: lbz 21, 311(1)
; PPC64BE-NEXT: std 28, -32(1) # 8-byte Folded Spill
; PPC64BE-NEXT: add 25, 22, 25
; PPC64BE-NEXT: lbz 28, 167(1)
@@ -212,7 +211,7 @@ define <16 x i8> @vector_i128_i8(<16 x i
; PPC64BE-NEXT: lbz 27, 159(1)
; PPC64BE-NEXT: lbz 24, 287(1)
; PPC64BE-NEXT: add 30, 29, 30
-; PPC64BE-NEXT: add 29, 23, 0
+; PPC64BE-NEXT: add 29, 21, 0
; PPC64BE-NEXT: addi 0, 29, 1
; PPC64BE-NEXT: add 28, 22, 28
; PPC64BE-NEXT: stb 0, 15(3)
@@ -228,7 +227,7 @@ define <16 x i8> @vector_i128_i8(<16 x i
; PPC64BE-NEXT: stb 0, 11(3)
; PPC64BE-NEXT: addi 0, 25, 1
; PPC64BE-NEXT: stb 12, 9(3)
-; PPC64BE-NEXT: addi 12, 2, 1
+; PPC64BE-NEXT: addi 12, 23, 1
; PPC64BE-NEXT: addi 11, 11, 1
; PPC64BE-NEXT: addi 10, 10, 1
; PPC64BE-NEXT: addi 9, 9, 1
@@ -247,7 +246,6 @@ define <16 x i8> @vector_i128_i8(<16 x i
; PPC64BE-NEXT: stb 6, 2(3)
; PPC64BE-NEXT: stb 5, 1(3)
; PPC64BE-NEXT: stb 4, 0(3)
-; PPC64BE-NEXT: ld 2, -96(1) # 8-byte Folded Reload
; PPC64BE-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; PPC64BE-NEXT: ld 29, -24(1) # 8-byte Folded Reload
; PPC64BE-NEXT: ld 28, -32(1) # 8-byte Folded Reload
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