[PATCH] D67487: [CodeEmitter] Support instruction widths > 64 bits

James Molloy via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Sep 12 03:25:47 PDT 2019


jmolloy created this revision.
jmolloy added reviewers: SjoerdMeijer, olista01, majnemer, ThomasRaoux.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Some VLIW instruction sets are Very Long Indeed. Using uint64_t constricts the Inst encoding to 64 bits (naturally).

This change switches CodeEmitter to a mode that uses APInts when Inst's bitwidth is > 64 bits (NFC for existing targets).

When Inst.BitWidth > 64 the prototype changes to:

  void TargetMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
                                                  SmallVectorImpl<MCFixup> &Fixups,
                                                  APInt &Inst,
                                                  APInt &Scratch,
                                                  const MCSubtargetInfo &STI);

The Inst parameter returns the encoded instruction, the Scratch parameter is used internally for manipulating operands and is exposed so that the underlying storage can be reused between calls to getBinaryCodeForInstr. The goal is to elide any APInt constructions that we can.

Similarly the operand encoding prototype changes to:

  getMachineOpValue(const MCInst &MI, const MCOperand &MO, APInt &op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI);

That is, the operand is passed by reference as APInt rather than returned as uint64_t.

To reiterate, this APInt mode is enabled only when Inst.BitWidth > 64, so this change is NFC for existing targets.


Repository:
  rL LLVM

https://reviews.llvm.org/D67487

Files:
  llvm/test/TableGen/BigEncoder.td
  llvm/test/TableGen/RegisterEncoder.td
  llvm/utils/TableGen/CodeEmitterGen.cpp

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