[PATCH] D67485: AArch64: use ldp/stp for atomic & volatile 128-bit where appropriate.

[Tim Northover via Phabricator via llvm-commits]

t.p.northover created this revision.
Herald added subscribers: jfb, hiraditya, kristof.beyls, mcrosier.
Herald added a project: LLVM.

>From v8.4a onwards, aligned 128-bit ldp and stp instructions are guaranteed to be single-copy atomic, so they are going to be a lot more efficient than the CAS loop we used to implement "load atomic" and "store atomic" before even if we do need a DMB sometimes. Additionally, some earlier CPUs had this property anyway so it makes sense to use it.

Finally, even before this guarantee there are machine-specific circumstances where a 128-bit ldp/stp makes sense but doesn't really fit an atomic profile. So this extends the selection to volatile accesses, even if they're not aligned (presumably the coder knows what they're doing). The one exception for volatile is when -mstrict-align is in force, that should take precedence.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D67485

Files:
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrAtomics.td
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/arm64-atomic-128.ll
  llvm/test/CodeGen/AArch64/cmpxchg-O0.ll
  llvm/test/CodeGen/AArch64/v8.4-atomic-128.ll
  llvm/test/CodeGen/AArch64/volatile-128.ll

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