[PATCH] D67397: [RISCV] Add MachineInstr immediate verification

[Luís Marques via Phabricator via llvm-commits]

luismarques updated this revision to Diff 219830.
luismarques added a comment.

Adds a MIR test. Changes the operand enum to a new namespace.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67397/new/

https://reviews.llvm.org/D67397

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
  llvm/test/CodeGen/RISCV/verify-instr.mir

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