[PATCH] D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill marked 3 inline comments as done.
lewis-revill added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/machineoutliner.mir:1-2
+# RUN: llc -march riscv32 -x mir < %s | FileCheck -check-prefix=RV32I %s
+# RUN: llc -march riscv32 -x mir -enable-machine-outliner < %s \
+# RUN: | FileCheck -check-prefix=RV32I-MO %s
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paquette wrote:
> You probably want -verify-machineinstrs on each of these.
I think there is some issue with the generation of MIR, at least for RISC-V... If I do IR -> MIR -> Assembly with -verify-machineinstrs, I get the error: 'Function has NoVRegs property but there are VReg operands'. I don't get it for IR -> Assembly with -verify-machineinstrs, and I'm not at all sure what to do about it.


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Comment at: llvm/test/CodeGen/RISCV/machineoutliner.mir:81
+    ; RV32I-MO-LABEL: outline_0:
+    ; RV32I-MO:         call t0, OUTLINED_FUNCTION_0
+    liveins: $x10, $x11
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paquette wrote:
> It would be good to check the contents of the outlined functions as well.
> 
> E.g. OUTLINED_FUNCTION_0 should contain the ORI/ADDI/AND sequence.
> 
> (It's possible that utils/update_mir_test_checks.py can generate all of the checks you want here, but I'm not sure if it can handle functions being created.)
> (It's possible that utils/update_mir_test_checks.py can generate all of the checks you want here, but I'm not sure if it can handle functions being created.)

I'm not sure I can either! Inserting check lines at the end of the file causes parsing errors.


Repository:
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  https://reviews.llvm.org/D66210/new/

https://reviews.llvm.org/D66210