[PATCH] D67259: [X86] Enable -mprefer-vector-width=256 by default for Skylake-avx512 and later Intel CPUs.

[Sanjay Patel via Phabricator via llvm-commits]

spatel accepted this revision.
spatel added a comment.
This revision is now accepted and ready to land.

LGTM



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Comment at: llvm/docs/ReleaseNotes.rst:100
+* -mprefer-vector-width=256 is now the default behavior skylake-avx512 and later
+  Intel CPUs. This tries to limit the use of 512-bit register which can cause a
+  decrease in CPU frequency on these CPUs. This can be re-enabled by passing
----------------
register -> registers


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67259/new/

https://reviews.llvm.org/D67259