[PATCH] D67433: [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Guillaume Chatelet via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 11 04:16:43 PDT 2019
This revision was automatically updated to reflect the committed changes.
Closed by commit rL371608: [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir… (authored by gchatelet, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D67433?vs=219684&id=219687#toc
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D67433/new/
https://reviews.llvm.org/D67433
Files:
llvm/trunk/include/llvm/CodeGen/MachineFunction.h
llvm/trunk/include/llvm/CodeGen/TargetLowering.h
llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/trunk/lib/CodeGen/AsmPrinter/WinException.cpp
llvm/trunk/lib/CodeGen/BranchRelaxation.cpp
llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
llvm/trunk/lib/CodeGen/MachineFunction.cpp
llvm/trunk/lib/CodeGen/PatchableFunction.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
llvm/trunk/lib/Target/AMDGPU/R600AsmPrinter.cpp
llvm/trunk/lib/Target/ARC/ARCMachineFunctionInfo.h
llvm/trunk/lib/Target/ARM/ARMBasicBlockInfo.cpp
llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp
llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp
llvm/trunk/lib/Target/SystemZ/SystemZLongBranch.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/combine-anyext-crash.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/fold-select.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ceil.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cos.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-exp.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fma.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-frint.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-round.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-trunc.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-1.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-2.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-log.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-log2.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-nearbyint.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sqrt.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-vector-icmp.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/localizer.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/observer-change-crash.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-binop.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-ctlz.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-frint.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-phi.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-select.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-store.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-stx.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-trap.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
llvm/trunk/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
llvm/trunk/test/CodeGen/AArch64/aarch64-vector-pcs.mir
llvm/trunk/test/CodeGen/AArch64/branch-relax-block-size.mir
llvm/trunk/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
llvm/trunk/test/CodeGen/AArch64/irg-nomem.mir
llvm/trunk/test/CodeGen/AArch64/jump-table-compress.mir
llvm/trunk/test/CodeGen/AArch64/machine-outliner-inline-asm-adrp.mir
llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir
llvm/trunk/test/CodeGen/AArch64/reverse-csr-restore-seq.mir
llvm/trunk/test/CodeGen/AArch64/spill-undef.mir
llvm/trunk/test/CodeGen/AArch64/wineh-frame0.mir
llvm/trunk/test/CodeGen/AArch64/wineh-frame1.mir
llvm/trunk/test/CodeGen/AArch64/wineh-frame2.mir
llvm/trunk/test/CodeGen/AArch64/wineh-frame3.mir
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llvm/trunk/test/CodeGen/AArch64/wineh-frame6.mir
llvm/trunk/test/CodeGen/AArch64/wineh-frame7.mir
llvm/trunk/test/CodeGen/AArch64/wineh-frame8.mir
llvm/trunk/test/CodeGen/AArch64/wineh1.mir
llvm/trunk/test/CodeGen/AArch64/wineh2.mir
llvm/trunk/test/CodeGen/AArch64/wineh3.mir
llvm/trunk/test/CodeGen/AArch64/wineh4.mir
llvm/trunk/test/CodeGen/AArch64/wineh5.mir
llvm/trunk/test/CodeGen/AArch64/wineh6.mir
llvm/trunk/test/CodeGen/AArch64/wineh7.mir
llvm/trunk/test/CodeGen/AArch64/wineh8.mir
llvm/trunk/test/CodeGen/AArch64/wineh_shrinkwrap.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
llvm/trunk/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
llvm/trunk/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
llvm/trunk/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
llvm/trunk/test/CodeGen/AMDGPU/fix-vgpr-copies.mir
llvm/trunk/test/CodeGen/AMDGPU/flat-load-clustering.mir
llvm/trunk/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
llvm/trunk/test/CodeGen/AMDGPU/hazard.mir
llvm/trunk/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir
llvm/trunk/test/CodeGen/AMDGPU/inserted-wait-states.mir
llvm/trunk/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
llvm/trunk/test/CodeGen/AMDGPU/limit-coalesce.mir
llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
llvm/trunk/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
llvm/trunk/test/CodeGen/AMDGPU/merge-load-store.mir
llvm/trunk/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
llvm/trunk/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
llvm/trunk/test/CodeGen/AMDGPU/schedule-regpressure.mir
llvm/trunk/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
llvm/trunk/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
llvm/trunk/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir
llvm/trunk/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
llvm/trunk/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
llvm/trunk/test/CodeGen/AMDGPU/wqm.mir
llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir
llvm/trunk/test/CodeGen/ARM/cmp1-peephole-thumb.mir
llvm/trunk/test/CodeGen/ARM/cmp2-peephole-thumb.mir
llvm/trunk/test/CodeGen/ARM/constant-island-movwt.mir
llvm/trunk/test/CodeGen/ARM/constant-islands-cfg.mir
llvm/trunk/test/CodeGen/ARM/constant-islands-split-IT.mir
llvm/trunk/test/CodeGen/ARM/dbg-range-extension.mir
llvm/trunk/test/CodeGen/ARM/expand-pseudos.mir
llvm/trunk/test/CodeGen/ARM/fp16-litpool-arm.mir
llvm/trunk/test/CodeGen/ARM/fp16-litpool-thumb.mir
llvm/trunk/test/CodeGen/ARM/fp16-litpool2-arm.mir
llvm/trunk/test/CodeGen/ARM/fp16-litpool3-arm.mir
llvm/trunk/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
llvm/trunk/test/CodeGen/ARM/misched-int-basic-thumb2.mir
llvm/trunk/test/CodeGen/ARM/misched-int-basic.mir
llvm/trunk/test/CodeGen/ARM/prera-ldst-aliasing.mir
llvm/trunk/test/CodeGen/ARM/prera-ldst-insertpt.mir
llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir
llvm/trunk/test/CodeGen/ARM/single-issue-r52.mir
llvm/trunk/test/CodeGen/ARM/v6-jumptable-clobber.mir
llvm/trunk/test/CodeGen/ARM/vldm-liveness.mir
llvm/trunk/test/CodeGen/ARM/vldmia-sched.mir
llvm/trunk/test/CodeGen/Hexagon/bank-conflict.mir
llvm/trunk/test/CodeGen/Hexagon/early-if-conv-lifetime.mir
llvm/trunk/test/CodeGen/Hexagon/early-if-predicator.mir
llvm/trunk/test/CodeGen/Hexagon/ifcvt-live-subreg.mir
llvm/trunk/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir
llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir
llvm/trunk/test/CodeGen/Lanai/peephole-compare.mir
llvm/trunk/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir
llvm/trunk/test/CodeGen/MIR/AArch64/return-address-signing.mir
llvm/trunk/test/CodeGen/MIR/AArch64/swp.mir
llvm/trunk/test/CodeGen/MIR/AMDGPU/syncscopes.mir
llvm/trunk/test/CodeGen/MIR/Generic/machine-function.mir
llvm/trunk/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir
llvm/trunk/test/CodeGen/MIR/PowerPC/prolog_vec_spills.mir
llvm/trunk/test/CodeGen/MIR/X86/branch-folder-with-label.mir
llvm/trunk/test/CodeGen/MIR/X86/diexpr-win32.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-stack-object.mir
llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-di.mir
llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
llvm/trunk/test/CodeGen/MIR/X86/frame-info-stack-references.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fabs.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/float_args.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/float_arithmetic_operations.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/float_constants.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fpext_and_fptrunc.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fptosi_and_fptoui.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address_pic.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/inttoptr_and_ptrtoint.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/sitofp_and_uitofp.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/store.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir
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