[PATCH] D67423: [RISCV] Consistently use Register arithmetic

[Luís Marques via Phabricator via llvm-commits]

luismarques added a comment.

In D67423#1665508 <https://reviews.llvm.org/D67423#1665508>, @jrtc27 wrote:

> It's worth noting that other targets (Mips and Sparc) call their floating point registers F0-F31 and D0-D31 (and there's also Q0-Q31 for Sparc) even though they're always referred to as `%fX` in the assembly. That would be an alternative resolution to the sorting issue, that also feels less hacky/surprising compared with the numerical-vs-alphabetical ordering subtleties.


Yeah, that's option #3 (with a different naming suggestion). I'm all for that, especially if there's a good precedent -- an existing naming convention for us to be consistent with.


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