[PATCH] D67162: [InstCombine] Known-bits optimization for ARM MVE VADC.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham marked 3 inline comments as done.
simon_tatham added inline comments.


================
Comment at: llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp:3334
+    Value *CarryArg = II->getArgOperand(CarryOp);
+    unsigned CarryWidth = CarryArg->getType()->getScalarSizeInBits();
+
----------------
dmgreen wrote:
> Is this ever not 32? If so the 32 below should be the same value
It should always be 32, because that intrinsic argument represents a value you can VMSR into FPSCR. I'll get rid of CarryWidth completely and make it an assertion.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67162/new/

https://reviews.llvm.org/D67162