[llvm] r371536 - AMDGPU/GlobalISel: RegBankSelect for G_ZEXTLOAD/G_SEXTLOAD
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 10 09:42:37 PDT 2019
Author: arsenm
Date: Tue Sep 10 09:42:37 2019
New Revision: 371536
URL: http://llvm.org/viewvc/llvm-project?rev=371536&view=rev
Log:
AMDGPU/GlobalISel: RegBankSelect for G_ZEXTLOAD/G_SEXTLOAD
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=371536&r1=371535&r2=371536&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Tue Sep 10 09:42:37 2019
@@ -780,7 +780,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
{S32, LocalPtr, 8, 8},
{S32, LocalPtr, 16, 16},
{S32, PrivatePtr, 8, 8},
- {S32, PrivatePtr, 16, 16}});
+ {S32, PrivatePtr, 16, 16},
+ {S32, ConstantPtr, 8, 8},
+ {S32, ConstantPtr, 16, 2 * 8}});
if (ST.hasFlatAddressSpace()) {
ExtLoads.legalForTypesWithMemDesc(
{{S32, FlatPtr, 8, 8}, {S32, FlatPtr, 16, 16}});
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=371536&r1=371535&r2=371536&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Tue Sep 10 09:42:37 2019
@@ -421,7 +421,9 @@ AMDGPURegisterBankInfo::getInstrAlternat
AltMappings.push_back(&VSMapping);
break;
}
- case TargetOpcode::G_LOAD: {
+ case TargetOpcode::G_LOAD:
+ case TargetOpcode::G_ZEXTLOAD:
+ case TargetOpcode::G_SEXTLOAD: {
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
LLT PtrTy = MRI.getType(MI.getOperand(1).getReg());
unsigned PtrSize = PtrTy.getSizeInBits();
@@ -1427,7 +1429,9 @@ void AMDGPURegisterBankInfo::applyMappin
}
break;
}
- case AMDGPU::G_LOAD: {
+ case AMDGPU::G_LOAD:
+ case AMDGPU::G_ZEXTLOAD:
+ case AMDGPU::G_SEXTLOAD: {
if (applyMappingWideLoad(MI, OpdMapper, MRI))
return;
break;
@@ -2321,6 +2325,8 @@ AMDGPURegisterBankInfo::getInstrMapping(
}
case AMDGPU::G_LOAD:
+ case AMDGPU::G_ZEXTLOAD:
+ case AMDGPU::G_SEXTLOAD:
return getInstrMappingForLoad(MI);
case AMDGPU::G_ATOMICRMW_XCHG:
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir?rev=371536&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir Tue Sep 10 09:42:37 2019
@@ -0,0 +1,98 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: sextload_constant_i8_to_i32_uniform
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+ ; CHECK-LABEL: name: sextload_constant_i8_to_i32_uniform
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p4) :: (load 1, addrspace 4)
+ %0:_(p4) = COPY $sgpr0_sgpr1
+ %1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 4, align 1)
+...
+
+---
+name: sextload_global_i8_to_i32_uniform
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: sextload_global_i8_to_i32_uniform
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p4) :: (load 1, addrspace 1)
+ %0:_(p4) = COPY $sgpr0_sgpr1
+ %1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 1, align 1)
+...
+
+---
+name: sextload_constant_i16_to_i32_uniform
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: sextload_constant_i16_to_i32_uniform
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p4) :: (load 2, addrspace 4)
+ %0:_(p4) = COPY $sgpr0_sgpr1
+ %1:_(s32) = G_SEXTLOAD %0 :: (load 2, addrspace 4, align 2)
+...
+
+---
+name: sextload_global_i16_to_i32_uniform
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: sextload_global_i16_to_i32_uniform
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p4) :: (load 2, addrspace 1)
+ %0:_(p4) = COPY $sgpr0_sgpr1
+ %1:_(s32) = G_SEXTLOAD %0 :: (load 2, addrspace 1, align 2)
+...
+
+---
+name: sextload_local_i8_to_i32_uniform
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: sextload_local_i8_to_i32_uniform
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p3) :: (load 1, addrspace 3)
+ %0:_(p3) = COPY $sgpr0
+ %1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 3, align 1)
+...
+
+---
+name: sextload_local_i16_to_i32_uniform
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; CHECK-LABEL: name: sextload_local_i16_to_i32_uniform
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p3) :: (load 2, addrspace 3)
+ %0:_(p3) = COPY $sgpr0
+ %1:_(s32) = G_SEXTLOAD %0 :: (load 2, addrspace 3, align 2)
+...
+!
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir?rev=371536&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir Tue Sep 10 09:42:37 2019
@@ -0,0 +1,97 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: zextload_constant_i8_to_i32_uniform
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+ ; CHECK-LABEL: name: zextload_constant_i8_to_i32_uniform
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p4) :: (load 1, addrspace 4)
+ %0:_(p4) = COPY $sgpr0_sgpr1
+ %1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 4, align 1)
+...
+
+---
+name: zextload_global_i8_to_i32_uniform
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: zextload_global_i8_to_i32_uniform
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p4) :: (load 1, addrspace 1)
+ %0:_(p4) = COPY $sgpr0_sgpr1
+ %1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 1, align 1)
+...
+
+---
+name: zextload_constant_i16_to_i32_uniform
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: zextload_constant_i16_to_i32_uniform
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p4) :: (load 2, addrspace 4)
+ %0:_(p4) = COPY $sgpr0_sgpr1
+ %1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 4, align 2)
+...
+
+---
+name: zextload_global_i16_to_i32_uniform
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: zextload_global_i16_to_i32_uniform
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p4) :: (load 2, addrspace 1)
+ %0:_(p4) = COPY $sgpr0_sgpr1
+ %1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 1, align 2)
+...
+
+---
+name: zextload_local_i8_to_i32_uniform
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: zextload_local_i8_to_i32_uniform
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p3) :: (load 1, addrspace 3)
+ %0:_(p3) = COPY $sgpr0
+ %1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 3, align 1)
+...
+
+---
+name: zextload_local_i16_to_i32_uniform
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; CHECK-LABEL: name: zextload_local_i16_to_i32_uniform
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p3) :: (load 2, addrspace 3)
+ %0:_(p3) = COPY $sgpr0
+ %1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 3, align 2)
+...
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