[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags
Sam Elliott via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 10 02:32:44 PDT 2019
lenary added a subscriber: luismarques.
lenary added a comment.
Nice, I like this new approach! One naming nit, but overall I think this is much better than the first version of the patch.
LGTM but I would like @luismarques to take a look too.
================
Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:49
RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
+ BitVector ReserveRegister;
RISCVFrameLowering FrameLowering;
----------------
Nit: Can this have a name that reveals it is for registers that are reserved by the user, rather than generally reserved?
We would like to differentiate `ra` being reserved because of the calling convention, vs `ra` being reserved because a user asked for `-ffixed-x1`.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D67185/new/
https://reviews.llvm.org/D67185
More information about the llvm-commits
mailing list