[PATCH] D67375: [ARM] VFPv2 only supports 16 D registers.

[Eli Friedman via Phabricator via llvm-commits]

efriedma created this revision.
efriedma added reviewers: simon_tatham, SjoerdMeijer, t.p.northover, ostannard, dmgreen.
Herald added subscribers: kristina, kristof.beyls.
Herald added a project: LLVM.

r361845 changed the way we handle "D16 <https://reviews.llvm.org/D16>" vs. "D32 <https://reviews.llvm.org/D32>" targets; there used to be a negative "d16" which removed instructions from the instruction set, and now there's a "d32" feature which adds instructions to the instruction set.  This is good, but there was an oversight in the implementation: the behavior of VFPv2 was changed.  In particular, the "vfp2" feature was changed to imply "d32". This is wrong: VFPv2 only supports 16 D registers.

In practice, this means if you specify -mfpu=vfpv2, the compiler will generate illegal instructions.

This patch gets rid of "vfp2d16" and "vfp2d16sp", and fixes "vfp2" and "vfp2sp" so they don't imply "d32".

(There are a couple minor corresponding changes to clang; I'll post a corresponding patch soon.)


Repository:
  rL LLVM

https://reviews.llvm.org/D67375

Files:
  lib/Object/ELFObjectFile.cpp
  lib/Support/ARMTargetParser.cpp
  lib/Target/ARM/ARM.td
  lib/Target/ARM/ARMPredicates.td
  lib/Target/ARM/ARMSubtarget.h
  lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
  test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
  test/CodeGen/ARM/build-attributes.ll
  test/CodeGen/ARM/inlineasm-X-allocation.ll
  test/CodeGen/ARM/softfp-constant-comparison.ll
  test/MC/ARM/vfp-aliases-diagnostics.s

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