[llvm] r371405 - [ARM] Remove some spurious MVE reduction instructions.
Simon Tatham via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 9 08:17:26 PDT 2019
Author: statham
Date: Mon Sep 9 08:17:26 2019
New Revision: 371405
URL: http://llvm.org/viewvc/llvm-project?rev=371405&view=rev
Log:
[ARM] Remove some spurious MVE reduction instructions.
The family of 'dual-accumulating' vector multiply-add instructions
(VMLADAV, VMLALDAV and VRMLALDAVH) can all operate on both signed and
unsigned integer types, and they all have an 'exchange' variant (with
an X in the name) that modifies which pairs of vector lanes in the two
inputs are multiplied together. But there's a clause in the spec that
says that the X variants //don't// operate on unsigned integer types,
only signed. You can have X, or unsigned, or neither, but not both.
We didn't notice that clause when we implemented the MC support for
these instructions, so LLVM believes that things like VMLADAVX.U8 do
exist, contradicting the spec. Here I fix that by conditioning them
out in Tablegen.
In order to do that, I've reversed the nesting order of the Tablegen
multiclasses for those instructions. Previously, the innermost
multiclass generated the X and not-X variants, and the one outside
that generated the A and not-A variants. Now X is done by the outer
multiclass, which allows me to bypass that one when I only want the
two not-X variants.
Changing the multiclass nesting order also changes the names of the
instruction ids unless I make a special effort not to. I decided that
while I was changing them anyway I'd make them look nicer; so now the
instructions have names like MVE_VMLADAVs32 or MVE_VMLADAVaxs32,
instead of cumbersome _noacc_noexch suffixes.
The corresponding multiply-subtract instructions are unaffected. Those
don't accept unsigned types at all, either in the spec or in LLVM.
Reviewers: ostannard, dmgreen
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67214
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
llvm/trunk/test/MC/ARM/mve-reductions.s
llvm/trunk/test/MC/Disassembler/ARM/mve-reductions.txt
Modified: llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrMVE.td?rev=371405&r1=371404&r2=371405&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrMVE.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrMVE.td Mon Sep 9 08:17:26 2019
@@ -700,56 +700,56 @@ class MVE_VMLAMLSDAV<string iname, strin
let Inst{0} = bit_0;
}
-multiclass MVE_VMLAMLSDAV_X<string iname, string suffix, dag iops, string cstr,
- bit sz, bit bit_28, bit A, bit bit_8, bit bit_0,
- list<dag> pattern=[]> {
- def _noexch : MVE_VMLAMLSDAV<iname, suffix, iops, cstr, sz,
- bit_28, A, 0b0, bit_8, bit_0, pattern>;
- def _exch : MVE_VMLAMLSDAV<iname # "x", suffix, iops, cstr, sz,
- bit_28, A, 0b1, bit_8, bit_0, pattern>;
-}
-
-multiclass MVE_VMLAMLSDAV_XA<string iname, string suffix, bit sz, bit bit_28,
- bit bit_8, bit bit_0, list<dag> pattern=[]> {
- defm _noacc : MVE_VMLAMLSDAV_X<iname, suffix, (ins MQPR:$Qn, MQPR:$Qm), "",
- sz, bit_28, 0b0, bit_8, bit_0, pattern>;
- defm _acc : MVE_VMLAMLSDAV_X<iname # "a", suffix,
- (ins tGPREven:$RdaSrc, MQPR:$Qn, MQPR:$Qm),
- "$RdaDest = $RdaSrc",
- sz, bit_28, 0b1, bit_8, bit_0, pattern>;
-}
-
-multiclass MVE_VMLADAV_multi<string suffix, bit sz, bit U, bit bit_8,
- list<dag> pattern=[]> {
- defm "" : MVE_VMLAMLSDAV_XA<"vmladav", suffix, sz, U, bit_8, 0b0, pattern>;
-}
-
-defm MVE_VMLADAVs16 : MVE_VMLADAV_multi<"s16", 0b0, 0b0, 0b0>;
-defm MVE_VMLADAVs32 : MVE_VMLADAV_multi<"s32", 0b1, 0b0, 0b0>;
-defm MVE_VMLADAVu16 : MVE_VMLADAV_multi<"u16", 0b0, 0b1, 0b0>;
-defm MVE_VMLADAVu32 : MVE_VMLADAV_multi<"u32", 0b1, 0b1, 0b0>;
+multiclass MVE_VMLAMLSDAV_A<string iname, string x, string suffix,
+ bit sz, bit bit_28, bit X, bit bit_8, bit bit_0,
+ list<dag> pattern=[]> {
+ def ""#x#suffix : MVE_VMLAMLSDAV<iname # x, suffix,
+ (ins MQPR:$Qn, MQPR:$Qm), "",
+ sz, bit_28, 0b0, X, bit_8, bit_0, pattern>;
+ def "a"#x#suffix : MVE_VMLAMLSDAV<iname # "a" # x, suffix,
+ (ins tGPREven:$RdaSrc, MQPR:$Qn, MQPR:$Qm),
+ "$RdaDest = $RdaSrc",
+ sz, bit_28, 0b1, X, bit_8, bit_0, pattern>;
+}
-defm MVE_VMLADAVs8 : MVE_VMLADAV_multi<"s8", 0b0, 0b0, 0b1>;
-defm MVE_VMLADAVu8 : MVE_VMLADAV_multi<"u8", 0b0, 0b1, 0b1>;
+multiclass MVE_VMLAMLSDAV_AX<string iname, string suffix, bit sz, bit bit_28,
+ bit bit_8, bit bit_0, list<dag> pattern=[]> {
+ defm "" : MVE_VMLAMLSDAV_A<iname, "", suffix, sz, bit_28,
+ 0b0, bit_8, bit_0, pattern>;
+ defm "" : MVE_VMLAMLSDAV_A<iname, "x", suffix, sz, bit_28,
+ 0b1, bit_8, bit_0, pattern>;
+}
-// vmlav aliases vmladav
-foreach acc = ["_acc", "_noacc"] in {
- foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32"] in {
- def : MVEInstAlias<!strconcat("vmlav", !if(!eq(acc, "_acc"), "a", ""),
- "${vp}.", suffix, "\t$RdaDest, $Qn, $Qm"),
- (!cast<Instruction>("MVE_VMLADAV"#suffix#acc#"_noexch")
- tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
- }
+multiclass MVE_VMLADAV_multi<string suffix, bit sz, bit bit_8,
+ list<dag> pattern=[]> {
+ defm "" : MVE_VMLAMLSDAV_AX<"vmladav", "s"#suffix,
+ sz, 0b0, bit_8, 0b0, pattern>;
+ defm "" : MVE_VMLAMLSDAV_A<"vmladav", "", "u"#suffix,
+ sz, 0b1, 0b0, bit_8, 0b0, pattern>;
}
multiclass MVE_VMLSDAV_multi<string suffix, bit sz, bit bit_28,
- list<dag> pattern=[]> {
- defm "" : MVE_VMLAMLSDAV_XA<"vmlsdav", suffix, sz, bit_28, 0b0, 0b1, pattern>;
+ list<dag> pattern=[]> {
+ defm "" : MVE_VMLAMLSDAV_AX<"vmlsdav", "s"#suffix,
+ sz, bit_28, 0b0, 0b1, pattern>;
}
-defm MVE_VMLSDAVs8 : MVE_VMLSDAV_multi<"s8", 0, 0b1>;
-defm MVE_VMLSDAVs16 : MVE_VMLSDAV_multi<"s16", 0, 0b0>;
-defm MVE_VMLSDAVs32 : MVE_VMLSDAV_multi<"s32", 1, 0b0>;
+defm MVE_VMLADAV : MVE_VMLADAV_multi< "8", 0b0, 0b1>;
+defm MVE_VMLADAV : MVE_VMLADAV_multi<"16", 0b0, 0b0>;
+defm MVE_VMLADAV : MVE_VMLADAV_multi<"32", 0b1, 0b0>;
+
+defm MVE_VMLSDAV : MVE_VMLSDAV_multi< "8", 0b0, 0b1>;
+defm MVE_VMLSDAV : MVE_VMLSDAV_multi<"16", 0b0, 0b0>;
+defm MVE_VMLSDAV : MVE_VMLSDAV_multi<"32", 0b1, 0b0>;
+
+// vmlav aliases vmladav
+foreach acc = ["", "a"] in {
+ foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32"] in {
+ def : MVEInstAlias<"vmlav"#acc#"${vp}."#suffix#"\t$RdaDest, $Qn, $Qm",
+ (!cast<Instruction>("MVE_VMLADAV"#acc#suffix)
+ tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+ }
+}
// Base class for VMLALDAV and VMLSLDAV, VRMLALDAVH, VRMLSLDAVH
class MVE_VMLALDAVBase<string iname, string suffix, dag iops, string cstr,
@@ -775,82 +775,83 @@ class MVE_VMLALDAVBase<string iname, str
let Inst{0} = bit_0;
}
-multiclass MVE_VMLALDAVBase_X<string iname, string suffix, dag iops,
- string cstr, bit sz, bit bit_28, bit A,
- bit bit_8, bit bit_0, list<dag> pattern=[]> {
- def _noexch : MVE_VMLALDAVBase<iname, suffix, iops, cstr, sz,
- bit_28, A, 0b0, bit_8, bit_0, pattern>;
- def _exch : MVE_VMLALDAVBase<iname # "x", suffix, iops, cstr, sz,
- bit_28, A, 0b1, bit_8, bit_0, pattern>;
+multiclass MVE_VMLALDAVBase_A<string iname, string x, string suffix,
+ bit sz, bit bit_28, bit X, bit bit_8, bit bit_0,
+ list<dag> pattern=[]> {
+ def ""#x#suffix : MVE_VMLALDAVBase<
+ iname # x, suffix, (ins MQPR:$Qn, MQPR:$Qm), "",
+ sz, bit_28, 0b0, X, bit_8, bit_0, pattern>;
+ def "a"#x#suffix : MVE_VMLALDAVBase<
+ iname # "a" # x, suffix,
+ (ins tGPREven:$RdaLoSrc, tGPROdd:$RdaHiSrc, MQPR:$Qn, MQPR:$Qm),
+ "$RdaLoDest = $RdaLoSrc,$RdaHiDest = $RdaHiSrc",
+ sz, bit_28, 0b1, X, bit_8, bit_0, pattern>;
}
-multiclass MVE_VMLALDAVBase_XA<string iname, string suffix, bit sz, bit bit_28,
- bit bit_8, bit bit_0, list<dag> pattern=[]> {
- defm _noacc : MVE_VMLALDAVBase_X<
- iname, suffix, (ins MQPR:$Qn, MQPR:$Qm), "",
- sz, bit_28, 0b0, bit_8, bit_0, pattern>;
- defm _acc : MVE_VMLALDAVBase_X<
- iname # "a", suffix, (ins tGPREven:$RdaLoSrc, tGPROdd:$RdaHiSrc,
- MQPR:$Qn, MQPR:$Qm),
- "$RdaLoDest = $RdaLoSrc,$RdaHiDest = $RdaHiSrc",
- sz, bit_28, 0b1, bit_8, bit_0, pattern>;
+
+multiclass MVE_VMLALDAVBase_AX<string iname, string suffix, bit sz, bit bit_28,
+ bit bit_8, bit bit_0, list<dag> pattern=[]> {
+ defm "" : MVE_VMLALDAVBase_A<iname, "", suffix, sz,
+ bit_28, 0b0, bit_8, bit_0, pattern>;
+ defm "" : MVE_VMLALDAVBase_A<iname, "x", suffix, sz,
+ bit_28, 0b1, bit_8, bit_0, pattern>;
}
-multiclass MVE_VRMLALDAVH_multi<string suffix, bit U, list<dag> pattern=[]> {
- defm "" : MVE_VMLALDAVBase_XA<
- "vrmlaldavh", suffix, 0b0, U, 0b1, 0b0, pattern>;
+multiclass MVE_VRMLALDAVH_multi<string suffix, list<dag> pattern=[]> {
+ defm "" : MVE_VMLALDAVBase_AX<"vrmlaldavh", "s"#suffix,
+ 0b0, 0b0, 0b1, 0b0, pattern>;
+ defm "" : MVE_VMLALDAVBase_A<"vrmlaldavh", "", "u"#suffix,
+ 0b0, 0b1, 0b0, 0b1, 0b0, pattern>;
}
-defm MVE_VRMLALDAVHs32 : MVE_VRMLALDAVH_multi<"s32", 0>;
-defm MVE_VRMLALDAVHu32 : MVE_VRMLALDAVH_multi<"u32", 1>;
+defm MVE_VRMLALDAVH : MVE_VRMLALDAVH_multi<"32">;
// vrmlalvh aliases for vrmlaldavh
def : MVEInstAlias<"vrmlalvh${vp}.s32\t$RdaLo, $RdaHi, $Qn, $Qm",
- (MVE_VRMLALDAVHs32_noacc_noexch
+ (MVE_VRMLALDAVHs32
tGPREven:$RdaLo, tGPROdd:$RdaHi,
MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
def : MVEInstAlias<"vrmlalvha${vp}.s32\t$RdaLo, $RdaHi, $Qn, $Qm",
- (MVE_VRMLALDAVHs32_acc_noexch
+ (MVE_VRMLALDAVHas32
tGPREven:$RdaLo, tGPROdd:$RdaHi,
MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
def : MVEInstAlias<"vrmlalvh${vp}.u32\t$RdaLo, $RdaHi, $Qn, $Qm",
- (MVE_VRMLALDAVHu32_noacc_noexch
+ (MVE_VRMLALDAVHu32
tGPREven:$RdaLo, tGPROdd:$RdaHi,
MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
def : MVEInstAlias<"vrmlalvha${vp}.u32\t$RdaLo, $RdaHi, $Qn, $Qm",
- (MVE_VRMLALDAVHu32_acc_noexch
+ (MVE_VRMLALDAVHau32
tGPREven:$RdaLo, tGPROdd:$RdaHi,
MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
-multiclass MVE_VMLALDAV_multi<string suffix, bit sz, bit U,
- list<dag> pattern=[]> {
- defm "" : MVE_VMLALDAVBase_XA<"vmlaldav", suffix, sz, U, 0b0, 0b0, pattern>;
+multiclass MVE_VMLALDAV_multi<string suffix, bit sz, list<dag> pattern=[]> {
+ defm "" : MVE_VMLALDAVBase_AX<"vmlaldav", "s"#suffix, sz, 0b0, 0b0, 0b0, pattern>;
+ defm "" : MVE_VMLALDAVBase_A<"vmlaldav", "", "u"#suffix,
+ sz, 0b1, 0b0, 0b0, 0b0, pattern>;
}
-defm MVE_VMLALDAVs16 : MVE_VMLALDAV_multi<"s16", 0b0, 0b0>;
-defm MVE_VMLALDAVs32 : MVE_VMLALDAV_multi<"s32", 0b1, 0b0>;
-defm MVE_VMLALDAVu16 : MVE_VMLALDAV_multi<"u16", 0b0, 0b1>;
-defm MVE_VMLALDAVu32 : MVE_VMLALDAV_multi<"u32", 0b1, 0b1>;
+defm MVE_VMLALDAV : MVE_VMLALDAV_multi<"16", 0b0>;
+defm MVE_VMLALDAV : MVE_VMLALDAV_multi<"32", 0b1>;
// vmlalv aliases vmlaldav
-foreach acc = ["_acc", "_noacc"] in {
+foreach acc = ["", "a"] in {
foreach suffix = ["s16", "s32", "u16", "u32"] in {
- def : MVEInstAlias<!strconcat("vmlalv", !if(!eq(acc, "_acc"), "a", ""),
- "${vp}.", suffix, "\t$RdaLoDest, $RdaHiDest, $Qn, $Qm"),
- (!cast<Instruction>("MVE_VMLALDAV"#suffix#acc#"_noexch")
+ def : MVEInstAlias<"vmlalv" # acc # "${vp}." # suffix #
+ "\t$RdaLoDest, $RdaHiDest, $Qn, $Qm",
+ (!cast<Instruction>("MVE_VMLALDAV"#acc#suffix)
tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest,
MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
}
}
multiclass MVE_VMLSLDAV_multi<string iname, string suffix, bit sz,
- bit bit_28, list<dag> pattern=[]> {
- defm "" : MVE_VMLALDAVBase_XA<iname, suffix, sz, bit_28, 0b0, 0b1, pattern>;
+ bit bit_28, list<dag> pattern=[]> {
+ defm "" : MVE_VMLALDAVBase_AX<iname, suffix, sz, bit_28, 0b0, 0b1, pattern>;
}
-defm MVE_VMLSLDAVs16 : MVE_VMLSLDAV_multi<"vmlsldav", "s16", 0b0, 0b0>;
-defm MVE_VMLSLDAVs32 : MVE_VMLSLDAV_multi<"vmlsldav", "s32", 0b1, 0b0>;
-defm MVE_VRMLSLDAVHs32 : MVE_VMLSLDAV_multi<"vrmlsldavh", "s32", 0b0, 0b1>;
+defm MVE_VMLSLDAV : MVE_VMLSLDAV_multi<"vmlsldav", "s16", 0b0, 0b0>;
+defm MVE_VMLSLDAV : MVE_VMLSLDAV_multi<"vmlsldav", "s32", 0b1, 0b0>;
+defm MVE_VRMLSLDAVH : MVE_VMLSLDAV_multi<"vrmlsldavh", "s32", 0b0, 0b1>;
// end of mve_rDest instructions
Modified: llvm/trunk/test/MC/ARM/mve-reductions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/mve-reductions.s?rev=371405&r1=371404&r2=371405&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/mve-reductions.s (original)
+++ llvm/trunk/test/MC/ARM/mve-reductions.s Mon Sep 9 08:17:26 2019
@@ -130,6 +130,42 @@ vmladavx.s16 r0, q0, q7
# CHECK: vmladavax.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x2e,0xfe]
vmladavax.s16 lr, q0, q7
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavax.u16 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavx.u16 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavax.u32 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavx.u32 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavax.u8 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavx.u8 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmlaldavax.u16 r2, r3, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmlaldavx.u16 r2, r3, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmlaldavax.u32 r2, r3, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmlaldavx.u32 r2, r3, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vrmlaldavhax.u32 r2, r3, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vrmlaldavhx.u32 r2, r3, q4, q5
+
# CHECK: vmlav.s8 lr, q3, q0 @ encoding: [0xf6,0xee,0x00,0xef]
vmladav.s8 lr, q3, q0
Modified: llvm/trunk/test/MC/Disassembler/ARM/mve-reductions.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/mve-reductions.txt?rev=371405&r1=371404&r2=371405&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/mve-reductions.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/mve-reductions.txt Mon Sep 9 08:17:26 2019
@@ -1,4 +1,5 @@
-# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s 2> %t | FileCheck %s
+# RUN: FileCheck --check-prefix=ERROR < %t %s
# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
@@ -182,6 +183,42 @@
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0xf0,0xee,0x2e,0xfe]
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf8,0xfe,0x2a,0x1e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf8,0xfe,0x0a,0x1e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf9,0xfe,0x2a,0x1e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf9,0xfe,0x0a,0x1e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf8,0xfe,0x2a,0x1f]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf8,0xfe,0x0a,0x1f]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfe,0x2a,0x3e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfe,0x0a,0x3e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x99,0xfe,0x2a,0x3e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x99,0xfe,0x0a,0x3e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfe,0x2a,0x3f]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfe,0x0a,0x3f]
+
# CHECK: vmlav.s8 lr, q3, q0 @ encoding: [0xf6,0xee,0x00,0xef]
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0xf6,0xee,0x00,0xef]
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