[PATCH] D67085: [ARM] Fix loads and stores for predicate vectors

[Dave Green via Phabricator via llvm-commits]

dmgreen updated this revision to Diff 219342.
dmgreen retitled this revision from "[ARM] Fix loads and stores for v4i1 and v8i1" to "[ARM] Fix loads and stores for predicate vectors".
dmgreen edited the summary of this revision.
dmgreen added a comment.

Now with v16i1, which doesn't need the extracts/buildvector, just going through the vmrs into a vstrh store.

This has the nice effect for bitcasts of eliding the load and store, giving us the bitcast lowering to vmsr for free (unfortunately the stack is still realigned. That should be fixable with a better preferred vector alignment though).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67085/new/

https://reviews.llvm.org/D67085

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
  llvm/test/CodeGen/Thumb2/mve-masked-load.ll
  llvm/test/CodeGen/Thumb2/mve-masked-store.ll
  llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
  llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll

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