[PATCH] D66939: [ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodings

[Oliver Stannard (Linaro) via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL371374: [ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodings (authored by ostannard, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D66939?vs=219117&id=219295#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66939/new/

https://reviews.llvm.org/D66939

Files:
  llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
  llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  llvm/trunk/test/MC/Disassembler/ARM/mve-scalar-shift-unpredictable.txt


Index: llvm/trunk/test/MC/Disassembler/ARM/mve-scalar-shift-unpredictable.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/mve-scalar-shift-unpredictable.txt
+++ llvm/trunk/test/MC/Disassembler/ARM/mve-scalar-shift-unpredictable.txt
@@ -0,0 +1,42 @@
+# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding %s 2> %t | FileCheck --check-prefix=CHECK %s
+# RUN: FileCheck --check-prefix=STDERR < %t %s
+
+[0x5e 0xea 0x6d 0xcf]
+# CHECK: sqrshr  lr, r12  @ encoding: [0x5e,0xea,0x2d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0xad 0xcf]
+# CHECK: sqrshr  lr, r12  @ encoding: [0x5e,0xea,0x2d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0xed 0xcf]
+# CHECK: sqrshr  lr, r12  @ encoding: [0x5e,0xea,0x2d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0x2d 0xce]
+# CHECK: sqrshr  lr, r12  @ encoding: [0x5e,0xea,0x2d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x51 0xea 0x2d 0x1f]
+# CHECK: sqrshr  r1, r1  @ encoding: [0x51,0xea,0x2d,0x1f]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0x4d 0xcf]
+# CHECK: uqrshl  lr, r12  @ encoding: [0x5e,0xea,0x0d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5b 0xea 0x8d 0xcf]
+# CHECK: uqrshl  r11, r12  @ encoding: [0x5b,0xea,0x0d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0xcd 0xcf]
+# CHECK: uqrshl  lr, r12  @ encoding: [0x5e,0xea,0x0d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5b 0xea 0x0d 0xce]
+# CHECK: uqrshl  r11, r12  @ encoding: [0x5b,0xea,0x0d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x53 0xea 0x0d 0x3f]
+# CHECK: uqrshl  r3, r3  @ encoding: [0x53,0xea,0x0d,0x3f]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
Index: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -6483,6 +6483,12 @@
     if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
       return MCDisassembler::Fail;
 
+    if (fieldFromInstruction (Insn, 6, 3) != 4)
+      return MCDisassembler::SoftFail;
+
+    if (Rda == Rm)
+      return MCDisassembler::SoftFail;
+
     return S;
   }
 
Index: llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
+++ llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
@@ -373,6 +373,8 @@
   let Inst{7-6} = 0b00;
   let Inst{5-4} = op5_4{1-0};
   let Inst{3-0} = 0b1101;
+
+  let Unpredictable{8-6} = 0b111;
 }
 
 def MVE_SQRSHR : MVE_ScalarShiftSRegReg<"sqrshr", 0b10>;


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