[llvm] r371374 - [ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodings

[Oliver Stannard via llvm-commits]

Author: ostannard
Date: Mon Sep  9 01:50:28 2019
New Revision: 371374

URL: http://llvm.org/viewvc/llvm-project?rev=371374&view=rev
Log:
[ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodings

Specify the Unpredictable bits, and return softfails when appropriate.

Patch by Mark Murray!

Differential revision: https://reviews.llvm.org/D66939

Added:
    llvm/trunk/test/MC/Disassembler/ARM/mve-scalar-shift-unpredictable.txt
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrMVE.td?rev=371374&r1=371373&r2=371374&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrMVE.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrMVE.td Mon Sep  9 01:50:28 2019
@@ -373,6 +373,8 @@ class MVE_ScalarShiftSRegReg<string inam
   let Inst{7-6} = 0b00;
   let Inst{5-4} = op5_4{1-0};
   let Inst{3-0} = 0b1101;
+
+  let Unpredictable{8-6} = 0b111;
 }
 
 def MVE_SQRSHR : MVE_ScalarShiftSRegReg<"sqrshr", 0b10>;

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=371374&r1=371373&r2=371374&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Sep  9 01:50:28 2019
@@ -6483,6 +6483,12 @@ static DecodeStatus DecodeMVEOverlapping
     if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
       return MCDisassembler::Fail;
 
+    if (fieldFromInstruction (Insn, 6, 3) != 4)
+      return MCDisassembler::SoftFail;
+
+    if (Rda == Rm)
+      return MCDisassembler::SoftFail;
+
     return S;
   }
 

Added: llvm/trunk/test/MC/Disassembler/ARM/mve-scalar-shift-unpredictable.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/mve-scalar-shift-unpredictable.txt?rev=371374&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/mve-scalar-shift-unpredictable.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/mve-scalar-shift-unpredictable.txt Mon Sep  9 01:50:28 2019
@@ -0,0 +1,42 @@
+# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding %s 2> %t | FileCheck --check-prefix=CHECK %s
+# RUN: FileCheck --check-prefix=STDERR < %t %s
+
+[0x5e 0xea 0x6d 0xcf]
+# CHECK: sqrshr  lr, r12  @ encoding: [0x5e,0xea,0x2d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0xad 0xcf]
+# CHECK: sqrshr  lr, r12  @ encoding: [0x5e,0xea,0x2d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0xed 0xcf]
+# CHECK: sqrshr  lr, r12  @ encoding: [0x5e,0xea,0x2d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0x2d 0xce]
+# CHECK: sqrshr  lr, r12  @ encoding: [0x5e,0xea,0x2d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x51 0xea 0x2d 0x1f]
+# CHECK: sqrshr  r1, r1  @ encoding: [0x51,0xea,0x2d,0x1f]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0x4d 0xcf]
+# CHECK: uqrshl  lr, r12  @ encoding: [0x5e,0xea,0x0d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5b 0xea 0x8d 0xcf]
+# CHECK: uqrshl  r11, r12  @ encoding: [0x5b,0xea,0x0d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0xcd 0xcf]
+# CHECK: uqrshl  lr, r12  @ encoding: [0x5e,0xea,0x0d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5b 0xea 0x0d 0xce]
+# CHECK: uqrshl  r11, r12  @ encoding: [0x5b,0xea,0x0d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x53 0xea 0x0d 0x3f]
+# CHECK: uqrshl  r3, r3  @ encoding: [0x53,0xea,0x0d,0x3f]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding