[llvm] r371345 - [X86] Use DAG.getConstant instead of getZeroVector in combinePMULDQ.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 8 12:24:43 PDT 2019
Author: ctopper
Date: Sun Sep 8 12:24:42 2019
New Revision: 371345
URL: http://llvm.org/viewvc/llvm-project?rev=371345&view=rev
Log:
[X86] Use DAG.getConstant instead of getZeroVector in combinePMULDQ.
getZeroVector canonicalizes the type to vXi32, but that's a
legalization action. We should use the most correct type if
possible.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=371345&r1=371344&r2=371345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Sep 8 12:24:42 2019
@@ -44768,7 +44768,7 @@ static SDValue combinePMULDQ(SDNode *N,
// Multiply by zero.
// Don't return RHS as it may contain UNDEFs.
if (ISD::isBuildVectorAllZeros(RHS.getNode()))
- return getZeroVector(N->getSimpleValueType(0), Subtarget, DAG, SDLoc(N));
+ return DAG.getConstant(0, SDLoc(N), N->getValueType(0));
// PMULDQ/PMULUDQ only uses lower 32 bits from each vector element.
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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