[PATCH] D65945: [LLVM][Alignment] Make functions using log of alignment explicit

[Guillaume Chatelet via Phabricator via llvm-commits]

gchatelet updated this revision to Diff 218868.
gchatelet added a comment.

- Rebasing
- Update documentation flags.
- Add missing renames
- Use powers of 2 for alignment in YAMLized mir files
- Make sure YAML MIR has align as Powers of 2. Fix tests.
- Added documentation in MIRLangRef.rst


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65945/new/

https://reviews.llvm.org/D65945

Files:
  llvm/docs/MIRLangRef.rst
  llvm/include/llvm/CodeGen/MachineBasicBlock.h
  llvm/include/llvm/CodeGen/MachineFunction.h
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/AsmPrinter/WinException.cpp
  llvm/lib/CodeGen/BranchRelaxation.cpp
  llvm/lib/CodeGen/MIRParser/MIParser.cpp
  llvm/lib/CodeGen/MIRParser/MIRParser.cpp
  llvm/lib/CodeGen/MIRPrinter.cpp
  llvm/lib/CodeGen/MachineBasicBlock.cpp
  llvm/lib/CodeGen/MachineBlockPlacement.cpp
  llvm/lib/CodeGen/MachineFunction.cpp
  llvm/lib/CodeGen/PatchableFunction.cpp
  llvm/lib/CodeGen/TargetLoweringBase.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
  llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.h
  llvm/lib/Target/ARC/ARCMachineFunctionInfo.h
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMBasicBlockInfo.cpp
  llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMSubtarget.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/AVR/AVRISelLowering.cpp
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp
  llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
  llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
  llvm/lib/Target/Lanai/LanaiISelLowering.cpp
  llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h
  llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
  llvm/lib/Target/Mips/MipsAsmPrinter.cpp
  llvm/lib/Target/Mips/MipsBranchExpansion.cpp
  llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
  llvm/lib/Target/Mips/MipsISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/Sparc/SparcISelLowering.cpp
  llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
  llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86RetpolineThunks.cpp
  llvm/lib/Target/XCore/XCoreISelLowering.cpp
  llvm/test/CodeGen/ARM/constant-island-movwt.mir
  llvm/test/CodeGen/ARM/fp16-litpool-arm.mir
  llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir
  llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir
  llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir
  llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
  llvm/test/CodeGen/PowerPC/block-placement.mir
  llvm/test/CodeGen/X86/tail-merge-after-mbp.mir
  llvm/test/DebugInfo/X86/debug-loc-offset.mir

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