[PATCH] D67259: [X86] Enable -mprefer-vector-width=256 by default for Skylake-avx512 and later Intel CPUs.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D67259#1661797 <https://reviews.llvm.org/D67259#1661797>, @atdt wrote:

> Thank you; this is good to see.
>
> > I believe gcc and icc both do something similar to this by default.
>
> That's right.
>  GCC: https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf#page=647 (section 17-78)
>  ICC has `-qopt-zmm-usage=low|high`, which defaults to 'low' for Skylake targets (section 17-73)
>
> Let's update older targets, too. The argument for preferring 128-bit on Haswell and Broadwell is even stronger: on these microarchs, cores executing 256-bit AVX can lower the frequency of other cores on the system.


Haswell/broadwell will require a separate patch. We don't have a feature flag that we can use and we probably need to scrub more test command lines.


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  https://reviews.llvm.org/D67259/new/

https://reviews.llvm.org/D67259