[PATCH] D67110: AMDGPU: Make VReg_1 size be 1

[Matt Arsenault via Phabricator via llvm-commits]

arsenm marked an inline comment as done.
arsenm added inline comments.


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Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:677
 def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
-  let Size = 32;
+  let Size = 1;
 }
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rampitec wrote:
> arsenm wrote:
> > rampitec wrote:
> > > arsenm wrote:
> > > > rampitec wrote:
> > > > > This is spill size. How does that work when spill size if 1?
> > > > VReg_1 should never be seen by a spill. This could also be rounded when spilling
> > > Why are you sure it will never be spilled?
> > > Also if it is never spilled why is this field even matter?
> > Because this is a hack that exists for SelectionDAG. All uses should be eliminated in SILowerI1Copies. It matters because TableGen uses this as one of the sort and selection field. Without it, it picks VReg_1 instead of VGPR_32 as the preferred 32-bit register class
> OK, makes sense. What about SReg_1 handling in the comment above, in the isRegister32()?
Contextually, I think that would already be illegal so I don't think this assert should worry about it. That would be a VGPR->SGPR copy that would error elsewhere


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https://reviews.llvm.org/D67110