[PATCH] D67269: [ARM] Add patterns for VSUB with q and r registers

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

LGTM. Nice one.



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Comment at: llvm/lib/Target/ARM/ARMInstrMVE.td:3628
 
+let Predicates = [HasMVEInt] in {
+  def : Pat<(v16i8 (sub (v16i8 MQPR:$val1), (v16i8 (ARMvdup GPR:$val2)))),
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You could combine this into the same Predicates block (it doesn't matter a lot either way). Up to you.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67269/new/

https://reviews.llvm.org/D67269