[PATCH] D67266: [X86][NFC] Add a `use-aa` feature.

Clement Courbet via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 6 05:41:30 PDT 2019


courbet created this revision.
courbet added reviewers: RKSimon, andreadb, craig.topper.
Herald added subscribers: ychen, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

This allows enabling useaa on the command-line and will allow enabling the
feature on a per-CPU basis where benchmarking shows improvements.

This is modelled after the ARM/AArch64 target.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D67266

Files:
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86Subtarget.h


Index: llvm/lib/Target/X86/X86Subtarget.h
===================================================================
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -427,6 +427,9 @@
   /// Use software floating point for code generation.
   bool UseSoftFloat = false;
 
+  /// Use alias analysis during code generation.
+  bool UseAA = false;
+
   /// The minimum alignment known to hold of the stack frame on
   /// entry to the function and which must be maintained by every function.
   unsigned stackAlignment = 4;
@@ -738,6 +741,7 @@
            X86ProcFamily == IntelTRM;
   }
   bool useSoftFloat() const { return UseSoftFloat; }
+  bool useAA() const override { return UseAA; }
 
   /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
   /// no-sse2). There isn't any reason to disable it if the target processor
Index: llvm/lib/Target/X86/X86.td
===================================================================
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -453,6 +453,10 @@
                                         "Merge branches to a three-way "
                                         "conditional branch">;
 
+// Enable use of alias analysis during code generation.
+def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
+                                    "Use alias analysis during codegen">;
+
 // Bonnell
 def ProcIntelAtom : SubtargetFeature<"", "X86ProcFamily", "IntelAtom", "">;
 // Silvermont


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