[PATCH] D67218: [AMDGPU] Mark s_barrier as having side effects but not accessing memory.

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
foad added reviewers: arsenm, dstuttard, tpr, nhaehnle.
Herald added subscribers: hiraditya, t-tye, yaxunl, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

This fixes poor scheduling in a function containing a barrier and a few
load instructions.

Without this fix, ScheduleDAGInstrs::buildSchedGraph adds an artificial
edge in the dependency graph from the barrier instruction to the exit
node representing live-out latency, with a latency of about 500 cycles.
Because of this it thinks the critical path through the graph also has
a latency of about 500 cycles. And because of that it does not think
that any of the load instructions are on the critical path, so it
schedules them with no regard for their (80 cycle) latency, which gives
poor results.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D67218

Files:
  llvm/include/llvm/IR/IntrinsicsAMDGPU.td
  llvm/lib/Target/AMDGPU/SOPInstructions.td
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
  llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
  llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
  llvm/test/CodeGen/AMDGPU/v_mac_f16.ll
  llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll

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