[PATCH] D67214: [ARM] Remove some spurious MVE reduction instructions.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham created this revision.
simon_tatham added reviewers: ostannard, dmgreen.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

The family of 'dual-accumulating' vector multiply-add instructions
(VMLADAV, VMLALDAV and VRMLALDAVH) can all operate on both signed and
unsigned integer types, and they all have an 'exchange' variant (with
an X in the name) that modifies which pairs of vector lanes in the two
inputs are multiplied together. But there's a clause in the spec that
says that the X variants //don't// operate on unsigned integer types,
only signed. You can have X, or unsigned, or neither, but not both.

We didn't notice that clause when we implemented the MC support for
these instructions, so LLVM believes that things like VMLADAVX.U8 do
exist, contradicting the spec. Here I fix that by conditioning them
out in Tablegen.

I've done that in the simplest possible way, by adding what's
effectively an 'if' statement in the appropriate level of the existing
nest of multiclasses. I thought about inverting it all so that the X /
not-X was handled in the outermost layer of multiclasses, and then
providing an alternative version that didn't include the X variant,
but decided to leave it alone because the nesting order of the
multiclasses is also controlling how the instruction names are built
up, and I didn't want to change those pointlessly.

The corresponding multiply-subtract instructions are unaffected. Those
don't accept unsigned types at all, either in the spec or in LLVM.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D67214

Files:
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/test/MC/ARM/mve-reductions.s
  llvm/test/MC/Disassembler/ARM/mve-reductions.txt

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