[llvm] r370979 - GlobalISel: Add basic legalization for G_BITREVERSE
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 4 13:46:15 PDT 2019
Author: arsenm
Date: Wed Sep 4 13:46:15 2019
New Revision: 370979
URL: http://llvm.org/viewvc/llvm-project?rev=370979&view=rev
Log:
GlobalISel: Add basic legalization for G_BITREVERSE
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=370979&r1=370978&r2=370979&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Wed Sep 4 13:46:15 2019
@@ -1470,6 +1470,24 @@ LegalizerHelper::widenScalar(MachineInst
Observer.changedInstr(MI);
return Legalized;
}
+ case TargetOpcode::G_BITREVERSE: {
+ Observer.changingInstr(MI);
+
+ Register DstReg = MI.getOperand(0).getReg();
+ LLT Ty = MRI.getType(DstReg);
+ unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
+
+ Register DstExt = MRI.createGenericVirtualRegister(WideTy);
+ widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
+ MI.getOperand(0).setReg(DstExt);
+ MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
+
+ auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits);
+ auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt);
+ MIRBuilder.buildTrunc(DstReg, Shift);
+ Observer.changedInstr(MI);
+ return Legalized;
+ }
case TargetOpcode::G_ADD:
case TargetOpcode::G_AND:
case TargetOpcode::G_MUL:
@@ -2826,6 +2844,7 @@ LegalizerHelper::fewerElementsVector(Mac
case G_FSIN:
case G_FSQRT:
case G_BSWAP:
+ case G_BITREVERSE:
case G_SDIV:
case G_SMIN:
case G_SMAX:
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=370979&r1=370978&r2=370979&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Wed Sep 4 13:46:15 2019
@@ -433,7 +433,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
.widenScalarToNextPow2(1, 32);
// TODO: Expand for > s32
- getActionDefinitionsBuilder(G_BSWAP)
+ getActionDefinitionsBuilder({G_BSWAP, G_BITREVERSE})
.legalFor({S32})
.clampScalar(0, S32, S32)
.scalarize(0);
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir?rev=370979&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir Wed Sep 4 13:46:15 2019
@@ -0,0 +1,157 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
+
+---
+name: bitreverse_s8
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; CHECK-LABEL: name: bitreverse_s8
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s8) = G_TRUNC %0
+ %2:_(s8) = G_BITREVERSE %1
+ %3:_(s32) = G_ANYEXT %2
+ $vgpr0 = COPY %3
+...
+
+---
+name: bitreverse_s16
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; CHECK-LABEL: name: bitreverse_s16
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s16) = G_BITREVERSE %1
+ %3:_(s32) = G_ANYEXT %2
+ $vgpr0 = COPY %3
+...
+
+---
+name: bitreverse_s24
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; CHECK-LABEL: name: bitreverse_s24
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s24) = G_TRUNC %0
+ %2:_(s24) = G_BITREVERSE %1
+ %3:_(s32) = G_ANYEXT %2
+ $vgpr0 = COPY %3
+...
+
+---
+name: bitreverse_s32
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; CHECK-LABEL: name: bitreverse_s32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY]]
+ ; CHECK: $vgpr0 = COPY [[BITREVERSE]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = G_BITREVERSE %0
+ $vgpr0 = COPY %1
+...
+
+---
+name: bitreverse_v2s16
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; CHECK-LABEL: name: bitreverse_v2s16
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+ ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
+ ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
+ ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+ ; CHECK: [[BITREVERSE1:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY2]]
+ ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE1]], [[C]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
+ ; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
+ %0:_(<2 x s16>) = COPY $vgpr0
+ %1:_(<2 x s16>) = G_BITREVERSE %0
+ $vgpr0 = COPY %1
+...
+
+---
+name: bitreverse_v2s32
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: bitreverse_v2s32
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+ ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[UV]]
+ ; CHECK: [[BITREVERSE1:%[0-9]+]]:_(s32) = G_BITREVERSE [[UV1]]
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[BITREVERSE]](s32), [[BITREVERSE1]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s32>) = G_BITREVERSE %0
+ $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: bitreverse_s64
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: bitreverse_s64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s64) = G_BITREVERSE [[COPY]]
+ ; CHECK: $vgpr0_vgpr1 = COPY [[BITREVERSE]](s64)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_BITREVERSE %0
+ $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: bitreverse_v2s64
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-LABEL: name: bitreverse_v2s64
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
+ ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s64) = G_BITREVERSE [[UV]]
+ ; CHECK: [[BITREVERSE1:%[0-9]+]]:_(s64) = G_BITREVERSE [[UV1]]
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[BITREVERSE]](s64), [[BITREVERSE1]](s64)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<2 x s64>) = G_BITREVERSE %0
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
+...
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