[llvm] r370937 - [X86] Pre-commit test cases and test run line changes for D67087
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 4 10:33:38 PDT 2019
Author: ctopper
Date: Wed Sep 4 10:33:38 2019
New Revision: 370937
URL: http://llvm.org/viewvc/llvm-project?rev=370937&view=rev
Log:
[X86] Pre-commit test cases and test run line changes for D67087
Modified:
llvm/trunk/test/CodeGen/X86/combine-sdiv.ll
llvm/trunk/test/CodeGen/X86/combine-srem.ll
llvm/trunk/test/CodeGen/X86/rem.ll
llvm/trunk/test/CodeGen/X86/srem-seteq.ll
llvm/trunk/test/CodeGen/X86/twoaddr-coalesce-3.ll
Modified: llvm/trunk/test/CodeGen/X86/combine-sdiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-sdiv.ll?rev=370937&r1=370936&r2=370937&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-sdiv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-sdiv.ll Wed Sep 4 10:33:38 2019
@@ -3106,3 +3106,148 @@ define <4 x i1> @boolvec_sdiv(<4 x i1> %
%r = sdiv <4 x i1> %x, %y
ret <4 x i1> %r
}
+
+define i32 @combine_sdiv_two(i32 %x) {
+; CHECK-LABEL: combine_sdiv_two:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shrl $31, %eax
+; CHECK-NEXT: addl %edi, %eax
+; CHECK-NEXT: sarl %eax
+; CHECK-NEXT: retq
+ %1 = sdiv i32 %x, 2
+ ret i32 %1
+}
+
+define i32 @combine_sdiv_negtwo(i32 %x) {
+; CHECK-LABEL: combine_sdiv_negtwo:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shrl $31, %eax
+; CHECK-NEXT: addl %edi, %eax
+; CHECK-NEXT: sarl %eax
+; CHECK-NEXT: negl %eax
+; CHECK-NEXT: retq
+ %1 = sdiv i32 %x, -2
+ ret i32 %1
+}
+
+define i8 @combine_i8_sdiv_pow2(i8 %x) {
+; CHECK-LABEL: combine_i8_sdiv_pow2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: sarb $7, %al
+; CHECK-NEXT: shrb $4, %al
+; CHECK-NEXT: addl %edi, %eax
+; CHECK-NEXT: sarb $4, %al
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = sdiv i8 %x, 16
+ ret i8 %1
+}
+
+define i8 @combine_i8_sdiv_negpow2(i8 %x) {
+; CHECK-LABEL: combine_i8_sdiv_negpow2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: sarb $7, %al
+; CHECK-NEXT: shrb $2, %al
+; CHECK-NEXT: addl %edi, %eax
+; CHECK-NEXT: sarb $6, %al
+; CHECK-NEXT: negb %al
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = sdiv i8 %x, -64
+ ret i8 %1
+}
+
+define i16 @combine_i16_sdiv_pow2(i16 %x) {
+; CHECK-LABEL: combine_i16_sdiv_pow2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movswl %di, %eax
+; CHECK-NEXT: shrl $27, %eax
+; CHECK-NEXT: andl $15, %eax
+; CHECK-NEXT: addl %edi, %eax
+; CHECK-NEXT: cwtl
+; CHECK-NEXT: shrl $4, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+ %1 = sdiv i16 %x, 16
+ ret i16 %1
+}
+
+define i16 @combine_i16_sdiv_negpow2(i16 %x) {
+; CHECK-LABEL: combine_i16_sdiv_negpow2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movswl %di, %eax
+; CHECK-NEXT: shrl $23, %eax
+; CHECK-NEXT: movzbl %al, %eax
+; CHECK-NEXT: addl %edi, %eax
+; CHECK-NEXT: cwtl
+; CHECK-NEXT: sarl $8, %eax
+; CHECK-NEXT: negl %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+ %1 = sdiv i16 %x, -256
+ ret i16 %1
+}
+
+define i32 @combine_i32_sdiv_pow2(i32 %x) {
+; CHECK-LABEL: combine_i32_sdiv_pow2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: sarl $31, %eax
+; CHECK-NEXT: shrl $28, %eax
+; CHECK-NEXT: addl %edi, %eax
+; CHECK-NEXT: sarl $4, %eax
+; CHECK-NEXT: retq
+ %1 = sdiv i32 %x, 16
+ ret i32 %1
+}
+
+define i32 @combine_i32_sdiv_negpow2(i32 %x) {
+; CHECK-LABEL: combine_i32_sdiv_negpow2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: sarl $31, %eax
+; CHECK-NEXT: shrl $24, %eax
+; CHECK-NEXT: addl %edi, %eax
+; CHECK-NEXT: sarl $8, %eax
+; CHECK-NEXT: negl %eax
+; CHECK-NEXT: retq
+ %1 = sdiv i32 %x, -256
+ ret i32 %1
+}
+
+define i64 @combine_i64_sdiv_pow2(i64 %x) {
+; CHECK-LABEL: combine_i64_sdiv_pow2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: sarq $63, %rax
+; CHECK-NEXT: shrq $60, %rax
+; CHECK-NEXT: addq %rdi, %rax
+; CHECK-NEXT: sarq $4, %rax
+; CHECK-NEXT: retq
+ %1 = sdiv i64 %x, 16
+ ret i64 %1
+}
+
+define i64 @combine_i64_sdiv_negpow2(i64 %x) {
+; CHECK-LABEL: combine_i64_sdiv_negpow2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: sarq $63, %rax
+; CHECK-NEXT: shrq $56, %rax
+; CHECK-NEXT: addq %rdi, %rax
+; CHECK-NEXT: sarq $8, %rax
+; CHECK-NEXT: negq %rax
+; CHECK-NEXT: retq
+ %1 = sdiv i64 %x, -256
+ ret i64 %1
+}
Modified: llvm/trunk/test/CodeGen/X86/combine-srem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-srem.ll?rev=370937&r1=370936&r2=370937&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-srem.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-srem.ll Wed Sep 4 10:33:38 2019
@@ -432,3 +432,139 @@ define <4 x i1> @boolvec_srem(<4 x i1> %
%r = srem <4 x i1> %x, %y
ret <4 x i1> %r
}
+
+define i32 @combine_srem_two(i32 %x) {
+; CHECK-LABEL: combine_srem_two:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: movl %edi, %ecx
+; CHECK-NEXT: shrl $31, %ecx
+; CHECK-NEXT: addl %edi, %ecx
+; CHECK-NEXT: andl $-2, %ecx
+; CHECK-NEXT: subl %ecx, %eax
+; CHECK-NEXT: retq
+ %1 = srem i32 %x, 2
+ ret i32 %1
+}
+
+define i32 @combine_srem_negtwo(i32 %x) {
+; CHECK-LABEL: combine_srem_negtwo:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: movl %edi, %ecx
+; CHECK-NEXT: shrl $31, %ecx
+; CHECK-NEXT: addl %edi, %ecx
+; CHECK-NEXT: andl $-2, %ecx
+; CHECK-NEXT: subl %ecx, %eax
+; CHECK-NEXT: retq
+ %1 = srem i32 %x, -2
+ ret i32 %1
+}
+
+define i8 @combine_i8_srem_negpow2(i8 %x) {
+; CHECK-LABEL: combine_i8_srem_negpow2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: movl %eax, %ecx
+; CHECK-NEXT: sarb $7, %cl
+; CHECK-NEXT: shrb $2, %cl
+; CHECK-NEXT: addb %al, %cl
+; CHECK-NEXT: andb $-64, %cl
+; CHECK-NEXT: subb %cl, %al
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = srem i8 %x, -64
+ ret i8 %1
+}
+
+define i16 @combine_i16_srem_pow2(i16 %x) {
+; CHECK-LABEL: combine_i16_srem_pow2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: movswl %ax, %ecx
+; CHECK-NEXT: shrl $27, %ecx
+; CHECK-NEXT: andl $15, %ecx
+; CHECK-NEXT: addl %edi, %ecx
+; CHECK-NEXT: andl $-16, %ecx
+; CHECK-NEXT: subl %ecx, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+ %1 = srem i16 %x, 16
+ ret i16 %1
+}
+
+define i16 @combine_i16_srem_negpow2(i16 %x) {
+; CHECK-LABEL: combine_i16_srem_negpow2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: movswl %ax, %ecx
+; CHECK-NEXT: shrl $23, %ecx
+; CHECK-NEXT: movzbl %cl, %ecx
+; CHECK-NEXT: addl %edi, %ecx
+; CHECK-NEXT: andl $-256, %ecx
+; CHECK-NEXT: subl %ecx, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+ %1 = srem i16 %x, -256
+ ret i16 %1
+}
+
+define i32 @combine_srem_pow2(i32 %x) {
+; CHECK-LABEL: combine_srem_pow2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: movl %edi, %ecx
+; CHECK-NEXT: sarl $31, %ecx
+; CHECK-NEXT: shrl $28, %ecx
+; CHECK-NEXT: addl %edi, %ecx
+; CHECK-NEXT: andl $-16, %ecx
+; CHECK-NEXT: subl %ecx, %eax
+; CHECK-NEXT: retq
+ %1 = srem i32 %x, 16
+ ret i32 %1
+}
+
+define i32 @combine_srem_negpow2(i32 %x) {
+; CHECK-LABEL: combine_srem_negpow2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: movl %edi, %ecx
+; CHECK-NEXT: sarl $31, %ecx
+; CHECK-NEXT: shrl $24, %ecx
+; CHECK-NEXT: addl %edi, %ecx
+; CHECK-NEXT: andl $-256, %ecx
+; CHECK-NEXT: subl %ecx, %eax
+; CHECK-NEXT: retq
+ %1 = srem i32 %x, -256
+ ret i32 %1
+}
+
+define i64 @combine_i64_srem_pow2(i64 %x) {
+; CHECK-LABEL: combine_i64_srem_pow2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: movq %rdi, %rcx
+; CHECK-NEXT: sarq $63, %rcx
+; CHECK-NEXT: shrq $60, %rcx
+; CHECK-NEXT: addq %rdi, %rcx
+; CHECK-NEXT: andq $-16, %rcx
+; CHECK-NEXT: subq %rcx, %rax
+; CHECK-NEXT: retq
+ %1 = srem i64 %x, 16
+ ret i64 %1
+}
+
+define i64 @combine_i64_srem_negpow2(i64 %x) {
+; CHECK-LABEL: combine_i64_srem_negpow2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: movq %rdi, %rcx
+; CHECK-NEXT: sarq $63, %rcx
+; CHECK-NEXT: shrq $56, %rcx
+; CHECK-NEXT: addq %rdi, %rcx
+; CHECK-NEXT: andq $-256, %rcx
+; CHECK-NEXT: subq %rcx, %rax
+; CHECK-NEXT: retq
+ %1 = srem i64 %x, -256
+ ret i64 %1
+}
Modified: llvm/trunk/test/CodeGen/X86/rem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/rem.ll?rev=370937&r1=370936&r2=370937&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/rem.ll (original)
+++ llvm/trunk/test/CodeGen/X86/rem.ll Wed Sep 4 10:33:38 2019
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+cmov | FileCheck %s
define i32 @test1(i32 %X) {
; CHECK-LABEL: test1:
Modified: llvm/trunk/test/CodeGen/X86/srem-seteq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/srem-seteq.ll?rev=370937&r1=370936&r2=370937&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/srem-seteq.ll (original)
+++ llvm/trunk/test/CodeGen/X86/srem-seteq.ll Wed Sep 4 10:33:38 2019
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=i686-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc -mtriple=i686-unknown-linux-gnu -mattr=+cmov < %s | FileCheck %s --check-prefixes=CHECK,X86
; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,X64
;------------------------------------------------------------------------------;
Modified: llvm/trunk/test/CodeGen/X86/twoaddr-coalesce-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/twoaddr-coalesce-3.ll?rev=370937&r1=370936&r2=370937&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/twoaddr-coalesce-3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/twoaddr-coalesce-3.ll Wed Sep 4 10:33:38 2019
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-- -relocation-model=pic | FileCheck %s
+; RUN: llc < %s -mtriple=i686-- -relocation-model=pic | FileCheck %s
; This test is to ensure the TwoAddrInstruction pass chooses the proper operands to
; merge and generates fewer mov insns.
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