[PATCH] D67148: [LoopVectorize][PowerPC] Estimate int and float register pressure separately in loop-vectorize

[Zixuan Wu (Zeson) via Phabricator via llvm-commits]

wuzish created this revision.
wuzish added reviewers: hfinkel, nemanjai, PowerPC, nadav, congh, chandlerc.
Herald added subscribers: llvm-commits, shchenz, zzheng, MaskRay, aheejin, hiraditya, jgravelle-google, sbc100, javed.absar, nhaehnle, jvesely, dschuff, arsenm, jholewinski.
Herald added a project: LLVM.

In loop-vectorize, interleave count and vector factor depend on target register number. Currently, it does not estimate the int and float type register pressure separately(especially for scalar type), so it's not accurate.

For POWER target, register num is special when VSX is enabled. When VSX is enabled, the number of int scalar register is 32(gpr), float is 64(vsr). But for int and float vector register both are 64(vsr).

I test it on POWER target, it makes huge performance improvement in one specific bmk and no other obvious degressions.


Repository:
  rL LLVM

https://reviews.llvm.org/D67148

Files:
  llvm/include/llvm/Analysis/TargetTransformInfo.h
  llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
  llvm/include/llvm/CodeGen/BasicTTIImpl.h
  llvm/lib/Analysis/TargetTransformInfo.cpp
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
  llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
  llvm/lib/Target/ARM/ARMTargetTransformInfo.h
  llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
  llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
  llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
  llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
  llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
  llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/lib/Target/X86/X86TargetTransformInfo.h
  llvm/lib/Target/XCore/XCoreTargetTransformInfo.h
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll
  llvm/test/Transforms/LoopVectorize/X86/reg-usage-debug.ll
  llvm/test/Transforms/LoopVectorize/X86/reg-usage.ll
  llvm/test/Transforms/LoopVectorize/unroll_novec.ll

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