[PATCH] D67158: [ARM] Add IR intrinsics for a sample of MVE instructions.

Simon Tatham via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 4 05:47:45 PDT 2019


simon_tatham created this revision.
simon_tatham added reviewers: dmgreen, miyuki, ostannard.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

This is a representative sample of the kind of IR intrinsics that
we'll need in order to implement the user-facing ACLE intrinsics for
MVE. We'll need a lot more like this to cover the whole MVE
instruction set, but this commit introduces an intrinsic or two from
lots of different categories:

- a vector gather load, with and without writeback
- an interleaving load and store
- a vector format conversion
- a vector-to-vector operation
- a vector-to-scalar reduction
- the unusual VADC instruction that also uses the FPSCR carry flag
- predicated versions of all of the above
- a scalar shift

Where possible, instruction selection for these intrinsics is done
using DAG ISel patterns. But if the intrinsic has to return multiple
values (writeback load, VADC producing the output carry) then the
selection has to be done in C++.

For the predicated intrinsics, we want to specify the predicate value
as a vector of the appropriate number of i1. So I've invented a sort
of 'subroutine' class in the Tablegen (you can write `mkpred<T>.p` to
get the predicate vector type that goes with a given value vector),
and also provided a couple of intrinsics to convert between those and
the integer form of the predicate as a C programmer will provide it.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D67158

Files:
  llvm/include/llvm/IR/IntrinsicsARM.td
  llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/test/CodeGen/Thumb2/mve-intrinsics/scalar-shifts.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/vadc.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/vaddq.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/vcvt.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/vld24.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/vldr.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/vminvq.ll

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