[PATCH] D67106: [ARM] Add patterns for BSWAP intrinsic on MVE

[oliver cruickshank via Phabricator via llvm-commits]

oliverlars created this revision.
oliverlars added reviewers: dmgreen, SjoerdMeijer, samparker, simon_tatham, t.p.northover.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

BSWAP can use the VREV instruction on MVE to produce better results than expanding.


Repository:
  rL LLVM

https://reviews.llvm.org/D67106

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/test/CodeGen/Thumb2/mve-bswap.ll


Index: llvm/test/CodeGen/Thumb2/mve-bswap.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Thumb2/mve-bswap.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve %s -o - | FileCheck %s
+
+define arm_aapcs_vfpcc <4 x i32> @bswap_4i32_t(<4 x i32> %src){
+; CHECK-LABEL: bswap_4i32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrev32.8 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+    %0 = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %src)
+    ret <4 x i32> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @bswap_8i16_t(<8 x i16> %src){
+; CHECK-LABEL: bswap_8i16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrev16.8 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+    %0 = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %src)
+    ret <8 x i16> %0
+}
+
+declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
+declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)
+
Index: llvm/lib/Target/ARM/ARMInstrMVE.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrMVE.td
+++ llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -1025,6 +1025,13 @@
 
 def MVE_VREV16_8  : MVE_VREV<"vrev16", "8", 0b00, 0b10>;
 
+let Predicates = [HasMVEInt] in {
+  def : Pat<(v8i16 (bswap (v8i16 MQPR:$src))),
+            (v8i16 (MVE_VREV16_8 (v8i16 MQPR:$src)))>;
+  def : Pat<(v4i32 (bswap (v4i32 MQPR:$src))),
+            (v4i32 (MVE_VREV32_8 (v4i32 MQPR:$src)))>;
+}
+
 let Predicates = [HasMVEInt] in {
   def : Pat<(v4i32 (ARMvrev64 (v4i32 MQPR:$src))),
             (v4i32 (MVE_VREV64_32 (v4i32 MQPR:$src)))>;
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -262,6 +262,7 @@
     setOperationAction(ISD::CTLZ, VT, Legal);
     setOperationAction(ISD::CTTZ, VT, Custom);
     setOperationAction(ISD::BITREVERSE, VT, Legal);
+    setOperationAction(ISD::BSWAP, VT, Legal);
 
     // No native support for these.
     setOperationAction(ISD::UDIV, VT, Expand);


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