[llvm] r370729 - [ARM][MVE] Decoding of VMSR doesn't diagnose some unpredictable encodings
Oliver Stannard via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 3 02:55:31 PDT 2019
Author: ostannard
Date: Tue Sep 3 02:55:30 2019
New Revision: 370729
URL: http://llvm.org/viewvc/llvm-project?rev=370729&view=rev
Log:
[ARM][MVE] Decoding of VMSR doesn't diagnose some unpredictable encodings
Decoding of VMSR doesn't diagnose some unpredictable encodings, as the unpredictable bits are not correctly set.
Diff-reduce this instruction's internals WRT VMRS so I can see the differences better. Mostly this is s/src/Rt/g.
Fill in the "should-be-(0)" bits.
Designate the Unpredictable{} bits for both VMRS and VMSR.
Patch by Mark Murray!
Differential revision: https://reviews.llvm.org/D66938
Added:
llvm/trunk/test/MC/Disassembler/ARM/vmrs-vmsr-invalid.txt
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=370729&r1=370728&r2=370729&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Sep 3 02:55:30 2019
@@ -2297,6 +2297,8 @@ class MovFromVFP<bits<4> opc19_16, dag o
let Inst{6-5} = 0b00;
let Inst{4} = 1;
let Inst{3-0} = 0b0000;
+ let Unpredictable{7-5} = 0b111;
+ let Unpredictable{3-0} = 0b1111;
}
let DecoderMethod = "DecodeForVMRSandVMSR" in {
@@ -2370,63 +2372,65 @@ class MovToVFP<bits<4> opc19_16, dag oop
VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
// Instruction operand.
- bits<4> src;
-
- // Encode instruction operand.
- let Inst{15-12} = src;
+ bits<4> Rt;
let Inst{27-20} = 0b11101110;
let Inst{19-16} = opc19_16;
+ let Inst{15-12} = Rt;
let Inst{11-8} = 0b1010;
let Inst{7} = 0;
+ let Inst{6-5} = 0b00;
let Inst{4} = 1;
+ let Inst{3-0} = 0b0000;
let Predicates = [HasVFP2];
+ let Unpredictable{7-5} = 0b111;
+ let Unpredictable{3-0} = 0b1111;
}
let DecoderMethod = "DecodeForVMRSandVMSR" in {
let Defs = [FPSCR] in {
let Predicates = [HasFPRegs] in
// Application level GPR -> FPSCR
- def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPRnopc:$src),
- "vmsr", "\tfpscr, $src",
- [(int_arm_set_fpscr GPRnopc:$src)]>;
+ def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPRnopc:$Rt),
+ "vmsr", "\tfpscr, $Rt",
+ [(int_arm_set_fpscr GPRnopc:$Rt)]>;
// System level GPR -> FPEXC
- def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPRnopc:$src),
- "vmsr", "\tfpexc, $src", []>;
+ def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPRnopc:$Rt),
+ "vmsr", "\tfpexc, $Rt", []>;
// System level GPR -> FPSID
- def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPRnopc:$src),
- "vmsr", "\tfpsid, $src", []>;
- def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPRnopc:$src),
- "vmsr", "\tfpinst, $src", []>;
- def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPRnopc:$src),
- "vmsr", "\tfpinst2, $src", []>;
+ def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPRnopc:$Rt),
+ "vmsr", "\tfpsid, $Rt", []>;
+ def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPRnopc:$Rt),
+ "vmsr", "\tfpinst, $Rt", []>;
+ def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPRnopc:$Rt),
+ "vmsr", "\tfpinst2, $Rt", []>;
}
let Predicates = [HasV8_1MMainline, Has8MSecExt] in {
// System level GPR -> FPSCR with context saving for security extensions
- def VMSR_FPCXTNS : MovToVFP<0b1110 /* fpcxtns */, (outs), (ins GPR:$src),
- "vmsr", "\tfpcxtns, $src", []>;
+ def VMSR_FPCXTNS : MovToVFP<0b1110 /* fpcxtns */, (outs), (ins GPR:$Rt),
+ "vmsr", "\tfpcxtns, $Rt", []>;
}
let Predicates = [HasV8_1MMainline, Has8MSecExt] in {
// System level GPR -> FPSCR with context saving for security extensions
- def VMSR_FPCXTS : MovToVFP<0b1111 /* fpcxts */, (outs), (ins GPR:$src),
- "vmsr", "\tfpcxts, $src", []>;
+ def VMSR_FPCXTS : MovToVFP<0b1111 /* fpcxts */, (outs), (ins GPR:$Rt),
+ "vmsr", "\tfpcxts, $Rt", []>;
}
let Predicates = [HasV8_1MMainline, HasFPRegs] in {
// System level GPR -> FPSCR_NZCVQC
def VMSR_FPSCR_NZCVQC
: MovToVFP<0b0010 /* fpscr_nzcvqc */,
- (outs cl_FPSCR_NZCV:$fpscr_out), (ins GPR:$src),
- "vmsr", "\tfpscr_nzcvqc, $src", []>;
+ (outs cl_FPSCR_NZCV:$fpscr_out), (ins GPR:$Rt),
+ "vmsr", "\tfpscr_nzcvqc, $Rt", []>;
}
let Predicates = [HasV8_1MMainline, HasMVEInt] in {
// System level GPR -> VPR/P0
let Defs = [VPR] in
- def VMSR_VPR : MovToVFP<0b1100 /* vpr */, (outs), (ins GPR:$src),
- "vmsr", "\tvpr, $src", []>;
+ def VMSR_VPR : MovToVFP<0b1100 /* vpr */, (outs), (ins GPR:$Rt),
+ "vmsr", "\tvpr, $Rt", []>;
- def VMSR_P0 : MovToVFP<0b1101 /* p0 */, (outs VCCR:$cond), (ins GPR:$src),
- "vmsr", "\tp0, $src", []>;
+ def VMSR_P0 : MovToVFP<0b1101 /* p0 */, (outs VCCR:$cond), (ins GPR:$Rt),
+ "vmsr", "\tp0, $Rt", []>;
}
}
Added: llvm/trunk/test/MC/Disassembler/ARM/vmrs-vmsr-invalid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/vmrs-vmsr-invalid.txt?rev=370729&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/vmrs-vmsr-invalid.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/vmrs-vmsr-invalid.txt Tue Sep 3 02:55:30 2019
@@ -0,0 +1,178 @@
+# RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext,+mve -show-encoding -disassemble < %s 2> %t | FileCheck --check-prefix=CHECK %s
+# RUN: FileCheck --check-prefix=STDERR < %t %s
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x11,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x12,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x13,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x14,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x15,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x16,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x17,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x18,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x19,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x1a,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x1b,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x1c,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x1d,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x1e,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x1f,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x30,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x50,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x70,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0x90,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0xb0,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0xd0,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+[0xe1,0xee,0xf0,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x11,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x12,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x13,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x14,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x15,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x16,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x17,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x18,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x19,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x1a,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x1b,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x1c,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x1d,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x1e,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x1f,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x30,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x50,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x70,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0x90,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0xb0,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0xd0,0x0a]
+
+# STDERR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+[0xf1,0xee,0xf0,0x0a]
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