[PATCH] D66938: [ARM][MVE] Decoding of VMSR doesn't diagnose some unpredictable encodings

[Mark Murray via Phabricator via llvm-commits]

MarkMurrayARM marked an inline comment as done.
MarkMurrayARM added inline comments.


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Comment at: lib/Target/ARM/ARMInstrVFP.td:2412
   let Inst{7}     = 0;
+  let Inst{6-5}   = 0b00;
   let Inst{4}     = 1;
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ostannard wrote:
> These lines could be collapsed together:
> 
>   let Inst{11-0} = 0b101000010000;
Sure, that would be shorter, but this way matches the way the bits are described in the official public documentation.If future decodings start to use these bits, then diffs should be less disruptive.

Also, this way matches the existing VMRS instruction.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D66938/new/

https://reviews.llvm.org/D66938