[PATCH] D66483: [ARM] Generate 8.1-m CSINC, CSNEG and CSINV instructions.

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:46
 
+extern cl::opt<bool> ARMGenerateCSEL;
+
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samparker wrote:
> Freaky way to control code gen! Do we really need this if code size is better and performance is on par or better..?
I think you are right. I've removed the option.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:4854
+        if (FVal == 0 && Opcode != ARMISD::CSINC) {
+          std::swap(TrueVal, FalseVal);
+          std::swap(TVal, FVal);
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samparker wrote:
> But FalseVal = TrueVal?
It does it the other way around in the future (D66701). I've moved that change here, and I think the swap makes it obvious that we are inverting the two conditions, even if we are about to throw one away.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66483/new/

https://reviews.llvm.org/D66483