[PATCH] D66703: [ARM] Ignore Implicit CPSR regs when lowering from Machine to MC operands

[Dave Green via Phabricator via llvm-commits]

dmgreen updated this revision to Diff 218378.
dmgreen added a comment.

I don't believe so, if I am understanding the question correctly.

- The csels will use ZR in the encoding usually meant for PC, so can't use PC directly.
- The asm/disass don't go through this codepath, which is just for lowering machine->mc (i.e only via codegen)
- So all the existing disassembly/assembly shouldn't be effected by this as far as I understand (none of the tests are complaining)
- And none of the codegen tests are failing either, so this doesn't seem to effect the asm output for anything that isn't csel.

We didn't seem to have tests for csel + pc though, so I've added some in the same place we were testing sp.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66703/new/

https://reviews.llvm.org/D66703

Files:
  llvm/lib/Target/ARM/ARMMCInstLower.cpp
  llvm/test/CodeGen/Thumb2/csel.ll
  llvm/test/CodeGen/Thumb2/mve-abs.ll
  llvm/test/CodeGen/Thumb2/mve-fmath.ll
  llvm/test/CodeGen/Thumb2/mve-minmax.ll
  llvm/test/CodeGen/Thumb2/mve-pred-and.ll
  llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
  llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
  llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
  llvm/test/CodeGen/Thumb2/mve-pred-not.ll
  llvm/test/CodeGen/Thumb2/mve-pred-or.ll
  llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
  llvm/test/CodeGen/Thumb2/mve-vcmp.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpr.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
  llvm/test/MC/ARM/thumbv8.1m.s

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