[llvm] r370667 - Partially revert D61491 "AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0"
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 2 07:40:57 PDT 2019
Author: foad
Date: Mon Sep 2 07:40:57 2019
New Revision: 370667
URL: http://llvm.org/viewvc/llvm-project?rev=370667&view=rev
Log:
Partially revert D61491 "AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0"
Summary:
D61491 caused us to use relocs when they're not strictly necessary, to
refer to symbols in the text section. This is a pessimization and it's a
problem for some loaders that don't support relocs yet.
Reviewers: nhaehnle, arsenm, tpr
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65813
Modified:
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/global-constant.ll
llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll
llvm/trunk/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=370667&r1=370666&r2=370667&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Mon Sep 2 07:40:57 2019
@@ -5030,11 +5030,8 @@ buildPCRelGlobalAddress(SelectionDAG &DA
// of the s_add_u32 instruction, we end up with an offset that is 4 bytes too
// small. This requires us to add 4 to the global variable offset in order to
// compute the correct address.
- unsigned LoFlags = GAFlags;
- if (LoFlags == SIInstrInfo::MO_NONE)
- LoFlags = SIInstrInfo::MO_REL32;
SDValue PtrLo =
- DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4, LoFlags);
+ DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4, GAFlags);
SDValue PtrHi;
if (GAFlags == SIInstrInfo::MO_NONE) {
PtrHi = DAG.getTargetConstant(0, DL, MVT::i32);
Modified: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp?rev=370667&r1=370666&r2=370667&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp Mon Sep 2 07:40:57 2019
@@ -514,7 +514,7 @@ bool isReadOnlySegment(const GlobalValue
}
bool shouldEmitConstantsToTextSection(const Triple &TT) {
- return TT.getOS() != Triple::AMDHSA;
+ return TT.getOS() == Triple::AMDPAL;
}
int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
Modified: llvm/trunk/test/CodeGen/AMDGPU/global-constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/global-constant.ll?rev=370667&r1=370666&r2=370667&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/global-constant.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/global-constant.ll Mon Sep 2 07:40:57 2019
@@ -1,5 +1,7 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOHSA %s
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA %s
+; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=PAL %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOPAL %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOPAL %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOPAL %s
@private1 = private unnamed_addr addrspace(4) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0]
@private2 = private unnamed_addr addrspace(4) constant [4 x float] [float 4.0, float 5.0, float 6.0, float 7.0]
@@ -8,23 +10,23 @@
; GCN-LABEL: {{^}}private_test:
; GCN: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
-; Non-HSA OSes use fixup into .text section.
-; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1
-; NOHSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], 0
-
-; HSA OSes use relocations.
-; HSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1 at rel32@lo+4
-; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], private1 at rel32@hi+4
+; PAL OSes use fixup into .text section.
+; PAL: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1
+; PAL: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], 0
+
+; Non-PAL OSes use relocations.
+; NOPAL: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1 at rel32@lo+4
+; NOPAL: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], private1 at rel32@hi+4
; GCN: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}
-; Non-HSA OSes use fixup into .text section.
-; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2
-; NOHSA: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], 0
-
-; HSA OSes use relocations.
-; HSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2 at rel32@lo+4
-; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], private2 at rel32@hi+4
+; PAL OSes use fixup into .text section.
+; PAL: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2
+; PAL: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], 0
+
+; Non-PAL OSes use relocations.
+; NOPAL: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2 at rel32@lo+4
+; NOPAL: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], private2 at rel32@hi+4
define amdgpu_kernel void @private_test(i32 %index, float addrspace(1)* %out) {
%ptr = getelementptr [4 x float], [4 x float] addrspace(4) * @private1, i32 0, i32 %index
@@ -36,10 +38,10 @@ define amdgpu_kernel void @private_test(
ret void
}
-; HSA-LABEL: {{^}}available_externally_test:
-; HSA: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
-; HSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], available_externally at gotpcrel32@lo+4
-; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], available_externally at gotpcrel32@hi+4
+; NOPAL-LABEL: {{^}}available_externally_test:
+; NOPAL: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
+; NOPAL: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], available_externally at gotpcrel32@lo+4
+; NOPAL: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], available_externally at gotpcrel32@hi+4
define amdgpu_kernel void @available_externally_test(i32 addrspace(1)* %out) {
%ptr = getelementptr [256 x i32], [256 x i32] addrspace(4)* @available_externally, i32 0, i32 1
%val = load i32, i32 addrspace(4)* %ptr
@@ -47,8 +49,8 @@ define amdgpu_kernel void @available_ext
ret void
}
-; NOHSA: .text
-; HSA: .section .rodata
+; PAL: .text
+; NOPAL: .section .rodata
; GCN: private1:
; GCN: private2:
Modified: llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll?rev=370667&r1=370666&r2=370667&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll Mon Sep 2 07:40:57 2019
@@ -2,7 +2,7 @@
; RUN: llc -march=amdgcn -mcpu=tonga -filetype=obj < %s | llvm-readobj -r --symbols | FileCheck %s -check-prefix=GCN
; RUN: llc -march=r600 -mcpu=cypress -filetype=obj < %s | llvm-readobj -r --symbols | FileCheck %s -check-prefix=EG
-; GCN: R_AMDGPU_REL32_LO extern_const_addrspace
+; GCN: R_AMDGPU_GOTPCREL32_LO extern_const_addrspace 0x0
; EG: R_AMDGPU_ABS32 extern_const_addrspace
; CHECK-DAG: Name: extern_const_addrspace
Modified: llvm/trunk/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll?rev=370667&r1=370666&r2=370667&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll Mon Sep 2 07:40:57 2019
@@ -4,13 +4,13 @@
; CHECK: Relocations [
; CHECK: Section (3) .rel.text {
-; CHECK: 0x58 R_AMDGPU_ABS32 .text 0x0
+; CHECK: 0x58 R_AMDGPU_ABS32 arr 0x0
; CHECK: }
; CHECK: ]
; CHECK: Symbol {
; CHECK: Name: arr (11)
-; CHECK: Value: 0x70
+; CHECK: Value: 0x0
; CHECK: Size: 16
; CHECK: Binding: Local (0x0)
; CHECK: Type: Object (0x1)
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