[PATCH] D66801: [X86][BtVer2] Fix latency and throughput of conditional SIMD store instructions.

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL370649: [X86][BtVer2] Fix latency and throughput of conditional SIMD store instructions. (authored by adibiagio, committed by ).
Herald added a project: LLVM.

Changed prior to commit:
  https://reviews.llvm.org/D66801?vs=218122&id=218339#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66801/new/

https://reviews.llvm.org/D66801

Files:
  llvm/trunk/lib/Target/X86/X86InstrSSE.td
  llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
  llvm/trunk/lib/Target/X86/X86SchedHaswell.td
  llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
  llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
  llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
  llvm/trunk/lib/Target/X86/X86Schedule.td
  llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
  llvm/trunk/lib/Target/X86/X86ScheduleBdVer2.td
  llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
  llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
  llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
  llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s
  llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-sse2.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D66801.218339.patch
Type: text/x-patch
Size: 24944 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190902/05b99dd6/attachment.bin>