[PATCH] D67070: [X86][SSE] Add support for <64 x i1> bool reduction

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, spatel.
Herald added a project: LLVM.

This generalizes the existing <32 x i1> pre-AVX2 split code to support reductions from <64 x i1> as well, we can probably generalize to any larger pow2 case in the future if the (unlikely) need ever arises.

We still need to tweak combineBitcastvxi1 to improve AVX512F codegen as its assumes vXi1 types should be handled on the mask registers even when they aren't legal.


Repository:
  rL LLVM

https://reviews.llvm.org/D67070

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/vector-reduce-and-bool.ll
  test/CodeGen/X86/vector-reduce-or-bool.ll
  test/CodeGen/X86/vector-reduce-xor-bool.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D67070.218329.patch
Type: text/x-patch
Size: 33677 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190902/660ea153/attachment.bin>