[PATCH] D67021: [DAGCombiner] improve throughput of shift+logic+shift

Sanjay Patel via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Sep 1 11:42:39 PDT 2019


This revision was automatically updated to reflect the committed changes.
spatel marked an inline comment as done.
Closed by commit rL370617: [DAGCombiner] improve throughput of shift+logic+shift (authored by spatel, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D67021?vs=218257&id=218271#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67021/new/

https://reviews.llvm.org/D67021

Files:
  llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/trunk/test/CodeGen/AArch64/bitfield-insert.ll
  llvm/trunk/test/CodeGen/AArch64/shift-logic.ll
  llvm/trunk/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll
  llvm/trunk/test/CodeGen/X86/shift-logic.ll

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